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PDF ICS9147-14 Data sheet ( Hoja de datos )
| Número de pieza | ICS9147-14 | |
| Descripción | Frequency Generator & Integrated Buffers | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
ICS9147 - 14
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
General Description
The ICS9147-14 generates all clocks required for high speed
RISC or CISC microprocessor systems such as Intel
PentiumPro.Two bidirectional I/O pins (FS1,FS2) are latched
at power-on to the functionality table, with FS0 selectable in
real-time to toggle between conditions.
High drive PCICLK and SDRAM outputs typically provide
greater than 1 V/ns slew rate into 30 pF loads. CPU outputs
typically provide better than 1V/ns slew rate into 20 pF loads
while maintaining50 ±5% duty cycle. The REF clock outputs
typically provide better than 0.5V/ns slew rates. Seperate
buffers supply pins VDDL1 allow for 3.3V or reduced voltage
swing (from 2.9 to 2.5V) for CPU (0:3) and IOAPIC outputs.
Block Diagram
Features
Four copies of CPU clock
Twelve SDRAM (3.3V TTL), usable asAGP clocks
Seven copies of PCICLK clock (synchronous with CPU
clock/2 or CPU/2.5 for 75 and 83.3 MHz CPU)
CPU clocks to PCICLK clocks skew 1-4ns, center 2.6ns.
One IOAPIC clock @14.31818MHz
Two copies of Ref. clock @14.31818MHz
Ref. 14.31818MHz Xtal oscillator input
Separate VDDL1 for four CPU and single IOAPIC output
buffers to allow 2.5V output (or Std. Vdd)
One each 48/ 24MHz (3.3V TTL)
3.3V outputs: SDRAM, PCI, REF, 48/24MHz.
2.5V or 3.3V outputs: CPU, IOAPIC.
20 ohm CPU clock output impedance
20 ohm PCI clock output impedance
1.5ns rise time (30 pF loading)
±250 ps CPU, PCI clock skew
350ps (cycle by cycle) CPU jitter
2ms Power up clock stable time
45-55% Clock duty cycle
48 pin 300 mil SSOP package
3.0V 3.7V supply range w/2.5V compatible outputs
Pin Configuration
Power Groups
VDD1 = REF (0:1), X1, X2, 24MHz, 48MHz
VDD2 = PCICLKF, PCICLK(0:5)
VDD3 = SDRAM (0;11)
VDDL1 = CPUCLK (0:3)
9147-14 Rev B 071897P
48-Pin SSOP
* Internal Pull-up Resistor of
300K to 3.3V on indicated inputs
Pentium is a trademark of Intel Corporation
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
1 page  
ICS9147 - 14
Shared Pin Operation -
Input/Output Pins
Pins 7, 8 and 26 on the ICS9147-14 serve as dual signal
functions to the device. During initial power-up, they act
as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 4-bit
internal data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered
clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm(10K) resistor is used to provide
both the solid CMOS programming voltage needed during
the power-up programming period and to provide an
insignificant load on the output clock during the subsequent
operating period.
Figs. 1 and 2 show the recommended means of
implementing this function. In Fig. 1 either one of the
resistors is loaded onto the board (selective stuffing) to
configure the devices internal logic. Figs. 2a and b provide
a single resistor loading option where either solder spot
tabs or a physical jumper header may be used.
These figures illustrate the optimal PCB physical layout
options. These configuration resistors are of such a large
ohmic value that they do not effect the low impedance
clock signals. The layouts have been optimized to provide
as little impedance transition to the clock signal as possible,
as it passes through the programming resistor pad(s).
Fig. 1
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