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PDF LXT301Z Data sheet ( Hoja de datos )
| Número de pieza | LXT301Z | |
| Descripción | (LXT300Z / LXT301Z) Advanced T1/E1 Short-Haul Transceivers | |
| Fabricantes | Intel | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LXT301Z (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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LXetT43U0.c0oZm/LXT301ZAdvanced T1/E1 Short-Haul Transceivers
She Datasheet
ta The LXT300Z and LXT301Z are fully integrated transceivers for both North American 1.544
a Mbps (T1) and International 2.048 Mbps (E1) applications. They are pin and functionally
.D compatible with standard LXT300/301 devices, with some circuit enhancements.
w The LXT300Z provides receive jitter attenuation starting at 3 Hz, and is microprocessor
w controllable through a serial interface. The LXT301Z is pin compatible, but does not provide
w jitter attenuation or a serial interface. An advanced transmit driver architecture provides constant
mlow output impedance for both marks and spaces, for improved Bit Error Rate performance over
various cable network configurations. Both transceivers offer a variety of diagnostic features
oincluding transmit and receive monitoring. Clock inputs may be derived from an on-chip crystal
oscillator or from digital inputs. They use an advanced double-poly, double-metal CMOS
.cprocess and require only a single 5-volt power supply.
Applications t4Us PCM/Voice Channel Banks
s Data Channel Bank/Concentrator
es T1/E1 multiplexers
s Digital Access and Cross-connect Systems
e(DACS)
s Computer to PBX interfaces (CPI & DMI)
s High-speed data transmission lines
s Interfacing Customer Premises Equipment
to a CSU
s Digital Loop Carrier (DLC) terminals
Product Features Shs Data recovery and clock recovery functions s Local and remote loopback functions
tas Receive jitter attenuation starting at 3 Hz
exceeds AT&T Pub 62411, Pub 43801, Pub
a43802, ITU G.703, and ITU G.823
(LXT300Z only)
.Ds Line driver with constant low mark and
space impedance (3 Ω typical)
s Minimum receive signal of 500 mV
ws Adaptive and selectable (E1/DSX-1) slicer
levels for improved SNR
s Programmable transmit equalizer shapes
wpulses to meet DSX-1 pulse template from
m0 to 655 feet or drive 120 Ω twisted pair or
w o75 Ω coax cable for E1
s Digital Transmit Driver Monitor
s Digital Receive Monitor with Loss of
Signal (LOS) output and first mark reset
s Receiver jitter tolerance 0.4 UI from 40
kHz to 100 kHz
s Microprocessor controllable (LXT300Z
only)
s Compatible with most popular PCM
framers
s Available in 28-pin DIP or PLCC
.DataSheet4U.cAs of January 15, 2001, this document replaces the Level One document
wwwLXT300Z/LXT301Z — Advanced T1/E1 Short-Haul Transceivers.
Order Number: 249066-001
January 2001
1 page  
Advanced T1/E1 Short-Haul Transceivers — LXT300Z/LXT301Z
Figure 1. LXT300Z/LXT301Z Block Diagram
MODE
HOS
T
INT
SDI
SDO
CS
SCLK
H/W
EC1
EC2
EC3
RLOOP
LLOOP
TAOS
TPOS
TNEG
TCLK
MCLK
XTALIN
XTALOUT
RCLK
RPOS
RNEG
LOS
DPM
Control
Equalizer
Synchronizer
Internal Clock
Generator
Jitter
Attenuator
Elastic
Store
Timing
Recovery
Constant Impedance
Line Driver
Data Slicers
Peak
Detector
TTIP
TRING
RTIP
RRING
Data
Latch
Receive
Monitor
Transmit
Driver
Control
MTIP
MRING
Datasheet
5
5 Page 
Advanced T1/E1 Short-Haul Transceivers — LXT300Z/LXT301Z
2.2.1
2.2.2
2.3
2.3.1
Receive (Loss of Signal) Monitor
The receive monitor generates a Loss of Signal (LOS) output upon receipt of 175 consecutive zeros
(spaces). The receiver monitor loads a digital counter at the RCLK frequency. The count is
incremented each time a zero is received, and reset to zero each time a one (mark) is received.
Upon receipt of 175 consecutive zeros the LOS pin goes High, and the RCLK output is replaced
with MCLK. LOS is reset when the first mark is received.
(In the LXT300Z only, if MCLK is not supplied, the RCLK output will be replaced with the centered
crystal clock.)
Jitter Attenuation (LXT300Z Only)
In the LXT300Z, recovered clock signals are supplied to the jitter attenuator and the data latch. The
recovered data is passed to the elastic store where it is buffered and synchronized with the
dejittered recovered clock (RCLK). Jitter attenuation of the LXT300Z clock and data outputs (see
Figure 5) is provided by a Jitter Attenuation Loop (JAL) and an Elastic Store (ES). An external
crystal oscillating at 4 times the bit rate provides clock stabilization. Refer to page 18 for crystal
specifications. The ES is a 32 x 2-bit register. Recovered data is clocked into the ES with the
recovered clock signal, and clocked out of the ES with the dejittered clock from the JAL. When the
bit count in the ES is within two bits of overflowing or underflowing, the ES adjusts the output
clock by 1/8 of a bit period. The ES produces an average delay of 16 bits in the receive path.
Transmitter
The transmitter circuits in the LXT300Z and LXT301Z are identical. The following discussion
applies to both devices. Data received for transmission onto the line is clocked serially into the
device at TPOS and TNEG. Input synchronization is supplied by the transmit clock (TCLK). The
transmitted pulse shape is determined by Equalizer Control signals EC1 through EC3 as shown in
Table 4. Refer to the “Test Specifications” section of this data sheet for master and transmit clock
timing characteristics. Shaped pulses are applied to the AMI line driver for transmission onto the
line at TTIP and TRING. Equalizer Control signals are hard-wired in the LXT301Z.
LXT300Z Only: Equalizer Control signals may be hardwired in the Hardware mode, or input as
part of the serial data stream (SDI) in the Host mode.
Pulses can be shaped for either 1.544 or 2.048 Mbps applications. DSX-1 applications with 1.544
Mbps pulses can be programmed to match line lengths from 0 to 655 feet of ABAM cable. The
LXT300Z and LXT301Z also match FCC specifications for CSU applications. Pulses at 2.048
Mbps can drive coaxial or shielded twisted-pair lines using appropriate resistors in line with the
output transformer.
Driver Performance Monitor
The transceiver incorporates an advanced Driver Performance Monitor (DPM) in parallel with the
TTIP and TRING at the output transformer. The DPM circuitry uses four comparators and a 150 ns
pulse discriminator to filter glitches. The DPM output level goes High upon detection of 63
consecutive zeros, and is cleared when a one is detected on the transmit line, or when a reset
command is received. The DPM output also goes High to indicate a ground on TTIP or TRING. A
ground fault induced DPM flag is automatically cleared when the ground condition is corrected
(chip reset is not required).
Datasheet
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LXT301Z.PDF ] | |
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