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PDF HD64F2623F Data sheet ( Hoja de datos )
| Número de pieza | HD64F2623F | |
| Descripción | (HD64F262x Series) 16-Bit Microcomputer | |
| Fabricantes | Hitachi | |
| Logotipo |  |
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To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
1 page  
General Precautions on the Handling of Products
1. Treatment of NC Pins
Note:
Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note:
Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass-
through current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note:
When power is first supplied, the product’s state is undefined. The states of internal
circuits are undefined until full power is supplied throughout the chip and a low level is
input on the reset pin. During the period where the states are undefined, the register
settings and the output state of each pin are also undefined. Design your system so that it
does not malfunction because of processing while it is in this undefined state. For those
products which have a reset function, reset the LSI immediately after the power supply has
been turned on.
4. Prohibition of Access to Undefined or Reserved Address
Note:
Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these address. Do not access these registers: the system’s
operation is not guaranteed if they are accessed.
5 Page 
Section
12.5.6 OVF Flag
Clearing in Interval
Timer Mode
Page
416
13.2.8 Bit Rate
Register (BRR)
436
Table 13-3 BRR
Settings for Various Bit
Rates (Asynchronous
Mode)
Table 13-4 BRR
Settings for Various Bit
Rates (Clocked
Synchronous Mode)
439
Table 13-5 Maximum
Bit Rate for Each
Frequency
(Asynchronous Mode)
441
Table 13-6 Maximum
Bit Rate with External
Clock Input
(Asynchronous Mode)
442
Table 13-7 Maximum
Bit Rate with External
Clock Input (Clocked
Synchronous Mode)
442
15.2.2 General Status 525
Register (GSR)
15.2.3 Bit
—
Configuration Register
(BCR)
Description
Newly added
12.5.6 OVF Flag Clearing in Interval Timer Mode
When the OVF Flag setting conflicts with the OVF flag reading in interval
timer mode, writing 0 to the OVF bit may not clear the flag even though the
OVF bit has been read while it is 1. If there is a possibility that the OVF flag
setting and reading will conflict, such as when the OVF flag is polled with the
interval timer interrupt disabled, read the OVF bit while it is 1 at least twice
before writing 0 to the OVF bit to clear the flag.
2 MHz, 2.097152 MHz, 2.4576 MHz, 3 MHz, and 3.6864 MHz columns of
table deleted
2 MHz column of table deleted
2 MHz, 2.097152 MHz, 2.4576 MHz, 3 MHz, and 3.6864 MHz rows of table
deleted
2 MHz, 2.097152 MHz, 2.4576 MHz, 3 MHz, and 3.6864 MHz rows of table
deleted
2 MHz row of table deleted
7th line changed as follows
The general status register (GSR) is an 8-bit readable register that indicates
the status of the CAN bus.
9th line changed as follows
Bits 7 to 4—Reserved: These bits always read 0.
15.3.2 Initialization after Hardware Reset
Detailed Description of One Bit of figure,
HCAN bit rate calculation,
BCR Setting Constraints,
Setting Range for TSEG1 and TSEG2 in BCR of table
Moved to Bit Rate and Bit Timing Settings
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet HD64F2623F.PDF ] | |
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