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PDF HD6432675 Data sheet ( Hoja de datos )
| Número de pieza | HD6432675 | |
| Descripción | (HD64F267x Series) 16-Bit Microcomputer | |
| Fabricantes | Hitachi | |
| Logotipo |  |
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To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
1 page  
General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note:
Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass-
through current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product’s state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses
Note:
Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system’s
operation is not guaranteed if they are accessed.
Rev. 2.0, 04/02, page iii of xliv
5 Page 
5.1 Features ....................................................................................................................... 85
5.2 Input/Output Pins ......................................................................................................... 86
5.3 Register Descriptions ................................................................................................... 87
5.3.1 Interrupt Control Register (INTCR) ................................................................. 87
5.3.2 Interrupt Priority Registers A to K (IPRA to IPRK).......................................... 88
5.3.3 IRQ Enable Register (IER) .............................................................................. 90
5.3.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ................................... 92
5.3.5 IRQ Status Register (ISR)................................................................................ 97
5.3.6 IRQ Pin Select Register (ITSR)........................................................................ 98
5.3.7 Software Standby Release IRQ Enable Register (SSIER).................................. 100
5.4 Interrupt Sources.......................................................................................................... 100
5.4.1 External Interrupts ........................................................................................... 100
5.4.2 Internal Interrupts ............................................................................................ 101
5.5 Interrupt Exception Handling Vector Table................................................................... 102
5.6 Interrupt Control Modes and Interrupt Operation .......................................................... 107
5.6.1 Interrupt Control Mode 0 ................................................................................. 107
5.6.2 Interrupt Control Mode 2 ................................................................................. 109
5.6.3 Interrupt Exception Handling Sequence ........................................................... 110
5.6.4 Interrupt Response Times ................................................................................ 112
5.6.5 DTC and DMAC Activation by Interrupt ......................................................... 113
5.7 Usage Notes.................................................................................................................116
5.7.1 Contention between Interrupt Generation and Disabling ................................... 116
5.7.2 Instructions that Disable Interrupts................................................................... 117
5.7.3 Times when Interrupts are Disabled ................................................................. 117
5.7.4 Interrupts during Execution of EEPMOV Instruction........................................ 117
5.7.5 Change of IRQ Pin Select Register (ITSR) Setting ........................................... 117
5.7.6 Note on IRQ Status Register (ISR)................................................................... 118
Section 6 Bus Controller (BSC) .....................................................................119
6.1 Features ....................................................................................................................... 119
6.2 Input/Output Pins ......................................................................................................... 121
6.3 Register Descriptions ................................................................................................... 123
6.3.1 Bus Width Control Register (ABWCR)............................................................ 124
6.3.2 Access State Control Register (ASTCR)........................................................... 124
6.3.3 Wait Control Registers AH, AL, BH, and BL
(WTCRAH, WTCRAL, WTCRBH, and WTCRBL)......................................... 125
6.3.4 Read Strobe Timing Control Register (RDNCR) .............................................. 130
6.3.5 &6 Assertion Period Control Registers H, L (CSACRH, CSACRL).................. 131
6.3.6 Area 0 Burst ROM Interface Control Register (BROMCRH)
Area 1 Burst ROM Interface Control Register (BROMCRL) ............................ 133
6.3.7 Bus Control Register (BCR)............................................................................. 134
6.3.8 DRAM Control Register (DRAMCR) .............................................................. 136
Rev. 2.0, 04/02, page ix of xliv
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HD6432675.PDF ] | |
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