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Analog Devices - 1.6 GHz Clock Distribution IC

Numéro de référence AD9515
Description 1.6 GHz Clock Distribution IC
Fabricant Analog Devices 
Logo Analog Devices 





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AD9515 fiche technique
Data Sheet
1.6 GHz Clock Distribution IC, Dividers,
Delay Adjust, Two Outputs
AD9515
FEATURES
1.6 GHz differential clock input
2 programmable dividers
Divide-by in range from1 to 32
Phase select for coarse delay adjust
1.6 GHz LVPECL clock output
Additive output jitter 225 fs rms
800 MHz/250 MHz LVDS/CMOS clock output
Additive output jitter 300 fs rms/290 fs rms
Time delays up to 10 ns
Device configured with 4-level logic pins
Space-saving, 32-lead LFCSP
APPLICATIONS
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
High performance instrumentation
Broadband infrastructure
ATE
GENERAL DESCRIPTION
The AD9515 features a two-output clock distribution IC in a
design that emphasizes low jitter and phase noise to maximize
data converter performance. Other applications with
demanding phase noise and jitter requirements also benefit
from this part.
There are two independent clock outputs. One output is
LVPECL, while the other output can be set to either LVDS or
CMOS levels. The LVPECL output operates to 1.6 GHz. The
other output operates to 800 MHz in LVDS mode and to
250 MHz in CMOS mode.
Each output has a programmable divider that can be set to
divide by a selected set of integers ranging from 1 to 32. The
phase of one clock output relative to the other clock output can
be set by means of a divider phase select function that serves as
a coarse timing adjustment.
CLK
CLKB
SYNCB
FUNCTIONAL BLOCK DIAGRAM
RSET
VS
GND
AD9515 LVPECL
/1. . . /32
OUT0
OUT0B
/1. . . /32
LVDS/CMOS
OUT1
t
OUT1B
SETUP LOGIC
VREF S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
Figure 1.
The LVDS/CMOS output features a delay element with three
selectable full-scale delay values (1.5 ns, 5 ns, and 10 ns), each
with 16 steps of fine adjustment.
The AD9515 does not require an external controller for
operation or setup. The device is programmed by means of
11 pins (S0 to S10) using 4-level logic. The programming pins
are internally biased to ⅓ VS. The VREF pin provides a level of
⅔ VS. VS (3.3 V) and GND (0 V) provide the other two logic levels.
The AD9515 is ideally suited for data converter clocking
applications where maximum converter performance is
achieved by encode signals with subpicosecond jitter.
The AD9515 is available in a 32-lead LFCSP and operates from
a single 3.3 V supply. The temperature range is −40°C to +85°C.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005–2012 Analog Devices, Inc. All rights reserved.

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