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PDF AD9513 Data sheet ( Hoja de datos )
| Número de pieza | AD9513 | |
| Descripción | 800 MHz Clock Distribution IC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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800 MHz Clock Distribution IC, Dividers,
Delay Adjust, Three Outputs
AD9513
FEATURES
1.6 GHz differential clock input
3 programmable dividers
Divide-by in range from1 to 32
Phase select for coarse delay adjust
Three 800 MHz/250 MHz LVDS/CMOS clock outputs
Additive output jitter 300 fs rms
Time delays up to 11.6 ns
Device configured with 4-level logic pins
Space-saving, 32-lead LFCSP
APPLICATIONS
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
High performance instrumentation
Broadband infrastructure
ATE
CLK
CLKB
SYNCB
FUNCTIONAL BLOCK DIAGRAM
RSET
VS
GND
/1. . . /32
AD9513
LVDS/CMOS
OUT0
OUT0B
/1. . . /32
LVDS/CMOS
OUT1
OUT1B
/1. . . /32
LVDS/CMOS
OUT2
∆t
OUT2B
SETUP LOGIC
VREF
S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
Figure 1.
GENERAL DESCRIPTION
The AD9513 features a three-output clock distribution IC in a
design that emphasizes low jitter and phase noise to maximize
data converter performance. Other applications with
demanding phase noise and jitter requirements also benefit
from this part.
There are three independent clock outputs that can be set to
either LVDS or CMOS levels. These outputs operate to
800 MHz in LVDS mode and to 250 MHz in CMOS mode.
Each output has a programmable divider that can be set to
divide by a selected set of integers ranging from 1 to 32. The
phase of one clock output relative to the other clock output can
be set by means of a divider phase select function that serves as
a coarse timing adjustment.
One of the outputs features a delay element with three selectable
full-scale delay values (1.8 ns, 6.0 ns, and 11.6 ns), each with
16 steps of fine adjustment.
The AD9513 does not require an external controller for
operation or setup. The device is programmed by means of
11 pins (S0 to S10) using 4-level logic. The programming pins
are internally biased to ⅓ VS. The VREF pin provides a level of
⅔ VS. VS (3.3 V) and GND (0 V) provide the other two logic levels.
The AD9513 is ideally suited for data converter clocking
applications where maximum converter performance is
achieved by encode signals with subpicosecond jitter.
The AD9513 is available in a 32-lead LFCSP and operates from
a single 3.3 V supply. The temperature range is −40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
1 page  
AD9513
TIMING CHARACTERISTICS
CLK input slew rate = 1 V/ns or greater.
Table 3.
Parameter
LVDS
Output Rise Time, tRL
Output Fall Time, tFL
PROPAGATION DELAY, tLVDS, CLK-TO-LVDS OUT
OUT0, OUT1, OUT2
Divide = 1
Divide = 2 − 32
Variation with Temperature
OUT2
Divide = 1
Divide = 2 − 32
Variation with Temperature
OUTPUT SKEW, LVDS OUTPUTS
OUT0 to OUT1 on Same Part, tSKV 1
OUT0 to OUT2 on Same Part, tSKV1
All LVDS OUTs Across Multiple Parts, tSKV_AB 2
Same LVDS OUTs Across Multiple Parts, tSKV_AB2
CMOS
Output Rise Time, tRC
Output Fall Time, tFC
PROPAGATION DELAY, tCMOS, CLK-TO-CMOS OUT
OUT0, OUT1
Divide = 1
Divide = 2 − 32
Variation with Temperature
OUT2
Divide = 1
Divide = 2 − 32
Variation with Temperature
OUTPUT SKEW, CMOS OUTPUTS
All CMOS OUTs on Same Part, tSKC1
All CMOS OUTs Across Multiple Parts, tSKC_AB2
Same CMOS OUTs Across Multiple Parts, tSKC_AB2
LVDS-TO-CMOS OUT
Output Skew, tSKV_C
DELAY ADJUST (OUT2; LVDS AND CMOS)
S0 = 1/3
Zero-Scale Delay Time3
Zero-Scale Variation with Temperature
Full-Scale Time Delay3
Full-Scale Variation with Temperature
S0 = 2/3
Zero-Scale Delay Time3
Zero-Scale Variation with Temperature
Full-Scale Time Delay3
Full-Scale Variation with Temperature
Min
1.03
1.09
1.07
1.13
−135
−205
1.14
1.19
1.20
1.24
−230
Typ Max Unit Test Conditions/Comments
Termination = 100 Ω differential
200 350 ps
20% to 80%, measured differentially
210 350 ps
80% to 20%, measured differentially
Delay off on OUT2
1.29 1.62 ns
1.35 1.68 ns
0.9 ps/°C
1.35 1.69 ns
1.41 1.75 ns
0.9 ps/°C
Delay off on OUT2
−20 +125 ps
−65 +90 ps
375 ps
300 ps
B outputs are inverted; termination = open
650 865 ps
20% to 80%; CLOAD = 3 pF
650 990 ps
80% to 20%; CLOAD = 3 pF
Delay off on OUT2
1.46 1.89 ns
1.51 1.94 ns
1 ps/°C
1.53 1.97 ns
1.57 2.01 ns
1 ps/°C
Delay off on OUT2
+135 ps
415 ps
330 ps
Everything the same; different logic type
510 ps
LVDS to CMOS on same part
0.35
0.20
1.8
−0.38
0.48
0.31
6.0
−1.3
ns
ps/°C
ns
ps/°C
ns
ps/°C
ns
ps/°C
Rev. 0 | Page 4 of 28
5 Page 
AD9513
TIMING DIAGRAMS
CLK
tCLK
tLVDS
tCMOS
Figure 2. CLK/CLKB to Clock Output Timing, DIV = 1 Mode
DIFFERENTIAL
80%
20%
LVDS
tRL tFL
Figure 3. LVDS Timing, Differential
SINGLE-ENDED
80%
20%
CMOS
3pF LOAD
tRC tFC
Figure 4. CMOS Timing, Single-Ended, 3 pF Load
Rev. 0 | Page 10 of 28
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet AD9513.PDF ] | |
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