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PDF AD9514 Data sheet ( Hoja de datos )
| Número de pieza | AD9514 | |
| Descripción | 1.6 GHz Clock Distribution IC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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1.6 GHz Clock Distribution IC,
Dividers, Delay Adjust, Three Outputs
AD9514
FEATURES
1.6 GHz differential clock input
3 programmable dividers
Divide-by in range from1 to 32
Phase select for coarse delay adjust
2 independent 1.6 GHz LVPECL clock outputs
Additive broadband output jitter 225 fs rms
1 independent 800 MHz/250 MHz LVDS/CMOS clock output
Additive broadband output jitter 300 fs rms/290 fs rms
Time delays up to 10 ns
Device configured with 4-level logic pins
Space-saving, 32-lead LFCSP
APPLICATIONS
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
High performance instrumentation
Broadband infrastructure
ATE
GENERAL DESCRIPTION
The AD9514 features a multi-output clock distribution IC in a
design that emphasizes low jitter and phase noise to maximize
data converter performance. Other applications with demanding
phase noise and jitter requirements also benefit from this part.
There are three independent clock outputs. Two of the outputs
are LVPECL, and the third output can be set to either LVDS or
CMOS levels. The LVPECL outputs operate to 1.6 GHz, and the
third output operates to 800 MHz in LVDS mode and to
250 MHz in CMOS mode.
Each output has a programmable divider that can be set to
divide by a selected set of integers ranging from 1 to 32. The
phase of one clock output relative to another clock output can
be set by means of a divider phase select function that serves as
a coarse timing adjustment.
CLK
CLKB
SYNCB
FUNCTIONAL BLOCK DIAGRAM
RSET
VS
GND
AD9514 LVPECL
/1. . . /32
OUT0
OUT0B
/1. . . /32
/1. . . /32
LVPECL
OUT1
OUT1B
LVDS/CMOS
OUT2
Δt
OUT2B
SETUP LOGIC
VREF S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
Figure 1.
The LVDS/CMOS output features a delay element with three
selectable full-scale delay values (1.5 ns, 5 ns, and 10 ns), each
with 16 steps of fine adjustment.
The AD9514 does not require an external controller for
operation or setup. The device is programmed by means of
11 pins (S0 to S10) using 4-level logic. The programming pins
are internally biased to ⅓ VS. The VREF pin provides a level of
⅔ VS. VS (3.3 V) and GND (0 V) provide the other two logic levels.
The AD9514 is ideally suited for data converter clocking
applications where maximum converter performance is
achieved by encode signals with subpicosecond jitter.
The AD9514 is available in a 32-lead LFCSP and operates from
a single 3.3 V supply. The temperature range is −40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
1 page  
AD9514
TIMING CHARACTERISTICS
CLK input slew rate = 1 V/ns or greater.
Table 3.
Parameter
LVPECL
Output Rise Time, tRP
Output Fall Time, tFP
PROPAGATION DELAY, tPECL, CLK-TO-LVPECL OUT
Divide = 1
Divide = 2 − 32
Variation with Temperature
OUTPUT SKEW, LVPECL
OUT0 to OUT1 on Same Part, tSKP1
Both LVPECL Outputs Across Multiple Parts, tSKP_AB2
Same LVPECL Output Across Multiple Parts, tSKP_AB2
LVDS
Output Rise Time, tRL
Output Fall Time, tFL
PROPAGATION DELAY, tLVDS, CLK-TO-LVDS OUT
Divide = 1
Divide = 2 − 32
Variation with Temperature
OUTPUT SKEW, LVDS
LVDS Output Across Multiple Parts, tSKV_AB2
CMOS
Output Rise Time, tRC
Output Fall Time, tFC
PROPAGATION DELAY, tCMOS, CLK-TO-CMOS OUT
Divide = 1
Divide = 2 − 32
Variation with Temperature
OUTPUT SKEW, CMOS
CMOS Output Across Multiple Parts, tSKC_AB2
LVPECL-TO-LVDS OUT
Output Delay, tSKV_C
LVPECL-TO-CMOS OUT
Output Delay, tSKV_C
DELAY ADJUST (OUT2; LVDS and CMOS)
S0 = 1/3
Zero Scale Delay Time3
Zero Scale Variation with Temperature
Full Scale Time Delay3
Full Scale Variation with Temperature
S0 = 2/3
Zero Scale Delay Time3
Zero Scale Variation with Temperature
Full Scale Time Delay3
Full Scale Variation with Temperature
Min Typ
60
60
Max Unit Test Conditions/Comments
Termination = 50 Ω to VS − 2 V
100 ps
20% to 80%, measured differentially
100 ps
80% to 20%, measured differentially
355 480
395 530
0.5
635 ps
710 ps
ps/°C
−50 0
200
210
1.00 1.25
1.05 1.30
0.9
650
650
1.10 1.45
1.15 1.50
1
+55 ps
125 ps
125 ps
Termination = 100 Ω differential, 3.5 mA
350 ps
20% to 80%, measured differentially
350 ps
80% to 20%, measured differentially
Optional delay off
1.55 ns
1.60 ns
ps/°C
Optional delay off
230 ps
B outputs are inverted; termination = open
865 ps
20% to 80%; CLOAD = 3 pF single-ended
990 ps
80% to 20%; CLOAD = 3 pF single-ended
Optional delay off
1.75 ns
1.80 ns
ps/°C
Optional delay off
300 ps
560 790 950 ps
700 970 1150 ps
0.34
0.20
1.7
−0.38
0.45
0.31
5.9
−1.3
ns
ps/°C
ns
ps/°C
ns
ps/°C
ns
ps/°C
Rev. 0 | Page 4 of 28
5 Page 
AD9514
SYNCB, VREF, AND SETUP PINS
Table 6.
Parameter
Min
SYNCB
Logic High
2.7
Logic Low
Capacitance
VREF
Output Voltage
0.62 VS
S0 TO S10
Levels
0
1/3 0.2 VS
2/3 0.55 VS
1 0.9 VS
Typ
2
Max
0.40
0.76 VS
0.1 VS
0.45 VS
0.8 VS
Unit Test Conditions/Comments
V
V
pF
V Minimum − maximum from 0 mA to 1 mA load
V
V
V
V
POWER
Table 7.
Parameter
Min Typ Max Unit Test Conditions/Comments
POWER-ON SYNCHRONIZATION1
35 ms See Figure 24.
VS Transit Time from 2.2 V to 3.1 V
POWER DISSIPATION
295 405 550 mW All outputs on. 2 LVPECL (divide = 2), 1 LVDS (divide = 2). No clock.
Does not include power dissipated in external resistors.
380 490 635 mW All outputs on. 2 LVPECL (divide = 2), 1 CMOS (divide = 2);
at 62.5 MHz out (5 pF load).
410 525 680 mW All outputs on. 2 LVPECL, 1 CMOS (divide = 2); At 125 MHz out (5 pF load).
POWER DELTA
Divider (Divide = 2 to Divide = 1) 15 30 45 mW For each divider. No clock.
LVPECL Output
65 90 125 mW For each output. No clock.
LVDS Output
20 50 85 mW No clock.
CMOS Output (Static)
30 40 50 mW No clock.
CMOS Output (@ 62.5 MHz)
80 110 140 mW Single-ended. At 62.5 MHz out with 5 pF load.
CMOS Output (@ 125 MHz)
110 150 190 mW Single-ended. At 125 MHz out with 5 pF load.
Delay Block
30 45 65 mW Off to 1.5 ns fs, delay word = 60; output clocking at 62.5 MHz.
1 This is the rise time of the VS supply that is required to ensure that a synchronization of the outputs occurs on power-up. The critical factor is the time it takes the VS to
transition the range from 2.2 V to 3 .1 V. If the rise time is too slow, the outputs will not be synchronized.
Rev. 0 | Page 10 of 28
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet AD9514.PDF ] | |
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