PDF AD9510 Data sheet ( Hoja de datos )

Número de pieza	AD9510
Descripción	1.2 GHz Clock Distribution IC
Fabricantes	Analog Devices
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Data Sheet 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs AD9510 FEATURES Low phase noise phase-locked loop core Reference input frequencies to 250 MHz Programmable dual modulus prescaler Programmable charge pump (CP) current Separate CP supply (VCPS) extends tuning range Two 1.6 GHz, differential clock inputs 8 programmable dividers, 1 to 32, all integers Phase select for output-to-output coarse delay adjust 4 independent 1.2 GHz LVPECL outputs Additive output jitter of 225 fs rms 4 independent 800 MHz low voltage differential signaling (LVDS) or 250 MHz complementary metal oxide conductor (CMOS) clock outputs Additive output jitter of 275 fs rms Fine delay adjust on 2 LVDS/CMOS outputs Serial control port Space-saving 64-lead LFCSP APPLICATIONS Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, and mixed-signal front ends (MxFEs) High performance wireless transceivers High performance instrumentation Broadband infrastructure GENERAL DESCRIPTION The AD9510 provides a multi-output clock distribution function along with an on-chip phase-locked loop (PLL) core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this device. The PLL section consists of a programmable reference divider (R); a low noise, phase frequency detector (PFD); a precision charge pump (CP); and a programmable feedback divider (N). By connecting an external voltage-controlled crystal oscillator (VCXO) or voltage-controlled oscillator (VCO) to the CLK2 and CLK2B pins, frequencies of up to 1.6 GHz can be synchronized to the input reference. There are eight independent clock outputs. Four outputs are low voltage positive emitter-coupled logic (LVPECL) at 1.2 GHz, and four are selectable as either LVDS (800 MHz) or CMOS (250 MHz) levels. REFIN REFINB FUNCTION CLK1 CLK1B SCLK SDIO SDO CSB FUNCTIONAL BLOCK DIAGRAM VS GND RSET CPRSET VCP DISTRIBUTION REF AD9510 SYNCB, RESETB PDB R DIVIDER N DIVIDER PHASE FREQUENCY DETECTOR PLL REF CHARGE PUMP PLL SETTINGS SERIAL CONTROL PORT PROGRAMMABLE DIVIDERS AND PHASE ADJUST /1, /2, /3... /31, /32 /1, /2, /3... /31, /32 /1, /2, /3... /31, /32 /1, /2, /3... /31, /32 /1, /2, /3... /31, /32 /1, /2, /3... /31, /32 ∆T /1, /2, /3... /31, /32 ∆T /1, /2, /3... /31, /32 LVPECL LVPECL LVPECL LVPECL LVDS/CMOS LVDS/CMOS LVDS/CMOS LVDS/CMOS Figure 1. CP STATUS CLK2 CLK2B OUT0 OUT0B OUT1 OUT1B OUT2 OUT2B OUT3 OUT3B OUT4 OUT4B OUT5 OUT5B OUT6 OUT6B OUT7 OUT7B Each output has a programmable divider that can be bypassed or set to divide by any integer up to 32. The phase of one clock output relative to another clock output can be varied by means of a divider phase select function that serves as a coarse timing adjustment. Two of the LVDS/CMOS outputs feature program- mable delay elements with full-scale ranges up to 8 ns of delay. This fine tuning delay block has 5-bit resolution, giving 25 possible delays from which to choose for each full-scale setting (Register 0x36 and Register 0x3A = 00000b to 11000b). The AD9510 is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter. The AD9510 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5.5 V. The temperature range is −40°C to +85°C. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2005–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page AD9510 Data Sheet SPECIFICATIONS Typical (typ) is given for VS = 3.3 V ± 5%, VS ≤ VCPS ≤ 5.5 V, TA = 25°C, RSET = 4.12 kΩ, CPRSET = 5.1 kΩ, unless otherwise noted. Minimum (min) and maximum (max) values are given over full VS and TA (−40°C to +85°C) variation. PLL CHARACTERISTICS Table 1. Parameter REFERENCE INPUTS (REFIN) Input Frequency Input Sensitivity Self-Bias Voltage, REFIN Self-Bias Voltage, REFINB Input Resistance, REFIN Input Resistance, REFINB Input Capacitance PHASE FREQUENCY DETECTOR (PFD) PFD Input Frequency PFD Input Frequency PFD Input Frequency Antibacklash Pulse Width Antibacklash Pulse Width Antibacklash Pulse Width CHARGE PUMP (CP) ICP Sink/Source High Value Low Value Absolute Accuracy CPRSET Range ICP Three-State Leakage Sink-and-Source Current Matching ICP vs. VCP ICP vs. Temperature RF CHARACTERISTICS (CLK2)2 Input Frequency Input Sensitivity Input Common-Mode Voltage, VCM Input Common-Mode Range, VCMR Input Sensitivity, Single-Ended Input Resistance Input Capacitance CLK2 VS. REFIN DELAY PRESCALER (PART OF N DIVIDER) Prescaler Input Frequency P = 2 DM (2/3) P = 4 DM (4/5) P = 8 DM (8/9) P = 16 DM (16/17) P = 32 DM (32/33) CLK2 Input Frequency for PLL Min Typ 0 150 1.45 1.60 1.40 1.50 4.0 4.9 4.5 5.4 2 1.3 2.9 6.0 4.8 0.60 2.5 2.7/10 1 2 1.5 2 150 1.5 1.6 1.3 150 4.0 4.8 2 500 Max Unit Test Conditions/Comments 250 MHz mV p-p 1.75 V Self-bias voltage of REFIN1 1.60 V Self-bias voltage of REFINB1 5.8 kΩ Self-biased1 6.3 kΩ Self-biased1 pF 100 MHz 100 MHz 45 MHz ns ns ns Antibacklash pulse width, Register 0x0D[1:0] = 00b Antibacklash pulse width, Register 0x0D[1:0] = 01b Antibacklash pulse width, Register 0x0D[1:0] = 10b Register 0x0D[1:0] = 00b (this is the default setting) Register 0x0D[1:0] = 01b Register 0x0D[1:0] = 10b Programmable mA With CPRSET = 5.1 kΩ mA % VCP = VCPS/2 kΩ nA % 0.5 < VCP < VCPS − 0.5 V % 0.5 < VCP < VCPS − 0.5 V % VCP = VCPS/2 V 1.6 GHz Frequencies > 1200 MHz (LVPECL) or 800 MHz (LVDS) require a minimum divide-by-2 (see the Distribution Section) mV p-p 1.7 V Self-biased, enables ac coupling 1.8 V With 200 mV p-p signal applied mV p-p CLK2 ac-coupled, CLK2B capacitively bypassed to RF ground 5.6 kΩ Self-biased pF ps Difference at PFD See the VCO/VCXO Feedback Divider—N (P, A, B) section 600 1000 1600 1600 1600 300 MHz MHz MHz MHz MHz MHz A, B counter input frequency Rev. C \| Page 4 of 56 5 Page AD9510 Parameter CLK1 = 245.76 MHz, OUT = 122.88 MHz Divide Ratio = 2 At 10 Hz Offset At 100 Hz Offset At 1 kHz Offset At 10 kHz Offset At 100 kHz Offset At 1 MHz Offset >10 MHz Offset CLK1-TO-CMOS ADDITIVE PHASE NOISE CLK1 = 245.76 MHz, OUT = 245.76 MHz Divide Ratio = 1 At 10 Hz Offset At 100 Hz Offset At 1 kHz Offset At 10 kHz Offset At 100 kHz Offset At 1 MHz Offset >10 MHz Offset CLK1 = 245.76 MHz, OUT = 61.44 MHz Divide Ratio = 4 At 10 Hz Offset At 100 Hz Offset At 1 kHz Offset At 10 kHz Offset At 100 kHz Offset At 1 MHz Offset >10 MHz Offset CLK1 = 78.6432 MHz, OUT = 78.6432 MHz Divide Ratio = 1 At 10 Hz Offset At 100 Hz Offset At 1 kHz Offset At 10 kHz Offset At 100 kHz Offset At 1 MHz Offset >10 MHz Offset CLK1 = 78.6432 MHz, OUT = 39.3216 MHz Divide Ratio = 2 At 10 Hz Offset At 100 Hz Offset At 1 kHz Offset At 10 kHz Offset At 100 kHz Offset >1 MHz Offset Min Typ Max Unit Data Sheet Test Conditions/Comments −118 −127 −137 −147 −154 −156 −158 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Distribution Section only, does not include PLL or external VCO/VCXO −110 −121 −130 −140 −145 −149 −156 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −122 −132 −143 −152 −158 −160 −162 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −122 −132 −140 −150 −155 −158 −160 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −128 −136 −146 −155 −161 −162 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Rev. C \| Page 10 of 56 11 Page

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