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PDF SAB80C515 Data sheet ( Hoja de datos )
| Número de pieza | SAB80C515 | |
| Descripción | 8-Bit Single-Chip Microcontroller Family | |
| Fabricantes | Siemens Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SAB80C515 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Microcomputer Components
SAB 80515/SAB 80C515
8-Bit Single-Chip Microcontroller Family
User's Manual 08.95
1 page  
Contents
Contents
Page
7.8 Oscillator and Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
7.8.1 Crystal Oscillator Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
7.8.2 Driving for External Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
7.8.2.1 Driving the SAB 80515/80535 from External Source . . . . . . . . . . . . . . . . . .108
7.8.2.2 Driving the SAB 80C515/80C535 from External Source . . . . . . . . . . . . . . .109
7.9 System Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
8 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
8.1 Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
8.2 Priority Level Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
8.3 How Interrupts are Handled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
8.4 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
8.5 Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
9
9.1
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.3
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
Introduction to the Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
Control Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
Instruction Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
10 Device Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
Semiconductor Group
5
5 Page 
Fundamental Structure
Central Processing Unit
The CPU is designed to operate on bits and bytes. The instructions, which consist of up to 3 bytes,
are performed in one, two or four machine cycles. One machine cycle requires twelve oscillator
cycles. The instruction set has extensive facilities for data transfer, logic and arithmetic instructions.
The Boolean processor has its own full-featured and bit-based instructions within the instruction set.
The SAB 80(C)515/80(C)535 uses five addressing modes: direct access, immediate, register,
register indirect access, and for accessing the external data or program memory portions a base
register plus index-register indirect addressing.
Memory Organization
The SAB 80C515, 80515 have an internal ROM of 8 Kbyte. The program memory can externally be
expanded up to 64 Kbyte (see bus expansion control). The internal RAM consists of 256 bytes.
Within this address space there are 128 bit-addressable locations and four register banks, each
with 8 general purpose registers. In addition to the internal RAM there is a further 128-byte address
space for the special function registers, which are described in sections to follow.
Because of its Harvard architecture, the SAB 80(C)515/80(C)535 distinguishes between an
external program memory portion (as mentioned above) and up to 64 Kbyte external data memory
accessed by a set of special instructions.
Bus Expansion Control
The external bus interface of the SAB 80(C)515/80(C)535 consists of an 8-bit data bus (port 0), a
16-bit address bus (port 0 and port 2) and five control lines. The address latch enable signal (ALE)
is used to demultiplex address and data of port 0. The program memory is accessed by the program
store enable signal (PSEN) twice a machine cycle. A separate external access line (EA) is used to
inform the controller while executing out of the lower 8 Kbyte of the program memory, whether to
operate out of the internal or external program memory. The read or write strobe (RD, WR) is used
for accessing the external data memory.
Peripheral Control
All on-chip peripheral components - I/O ports, serial interface, timers, compare/capture registers,
the interrupt controller and the A/D converter - are handled and controlled by the so-called special
function registers. These registers constitute the easy-to-handle interface with the peripherals. This
peripheral control concept, as implemented in the SAB 8051, provides the high flexibility for further
expansion as done in the SAB 80(C)515/80(C)535.
Moreover some of the special function registers, like accumulator, B-register, program status word
(PSW), stack pointer (SP) and the data pointer (DPTR) are used by the CPU and maintain the
machine status.
Semiconductor Group
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SAB80C515.PDF ] | |
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