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TDK - (75T202 / 75T203) 5V Low Power DTMF Receiver

Numéro de référence 75T203
Description (75T202 / 75T203) 5V Low Power DTMF Receiver
Fabricant TDK 
Logo TDK 





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75T203 fiche technique
taSheet4U.com D5TVML7F5oTRw2e-0Pc2eo/iw2v0ee3rrDESCRIPTION
aThe 75T202 and 75T203 are complete Dual-tone
.DMultifrequency (DTMF) receivers detecting a
wselectable group of 12 or 16 standard digits. No
wfront-end pre-filtering is needed. The only externally
wrequired components are an inexpensive 3.58 MHz
television “colorburs” crystal (for frequency
mreference) and a bias resistor. Extremely high
osystem density is made possible by using the clock
output of a crystal-connected 75T202 or 75T203
.creceiver to drive the time bases of additional
receivers. Both are monolithic integrated circuits
fabricated with low-power, complementary symmetry
UMOS (CMOS) processing. They require only a single
low tolerance voltage supply and are packaged in a
t4standard 18-pin plastic DIP.
(continued)
FEATURES
February 1998
Central office quality
NO front-end band-splitting filters required
Single, low-tolerance, 5-volt supply
Detects either 12 or 16 standard DTMF digits
Uses inexpensive 3.579545 MHz crystal for
reference
Excellent speech immunity
Output in either 4-bit hexadecimal code or binary
coded 2-of-8
18-pin DIP package for high system density
Synchronous or handshake interface
Three-state outputs
Early detect output (75T203 only)
eeBLOCK DIAGRAM
taShANALOG
PRE-PROCESSOR
60 Hz
REJECT
PREEMP
w.DaATB
XEN
wXIN
w m1Mz
U.coXOUT
÷8
BAND
SPLIT
FILTERS
BS1
ZERO
CROSSING
DETECTORS
BS2
CLOCK
GENERATOR
BANDPASS FILTERS
697
770
852
941
1209
1336
1477
1633
CHIP CLOCKS
AMPLITUDE
DETECTORS
TIMING
CIRCUITRY
DV
DATA STROBE
CLR
DV
F.F.
OUTPUT
DECODER
OUTPUT
REGISTER
eet4POWER REGULATOR
www.DataShVP GND GND
VOLTAGE
REF
DATA CLEAR
IN1633
ED 75T203
CLRDV
DV
HEX/B28
D1
D2
D4
D8
EN

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