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PDF ICS952607 Data sheet ( Hoja de datos )
| Número de pieza | ICS952607 | |
| Descripción | Programmable Timing Control Hub for Next Gen P4 processor | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS952607
Advance Information
Programmable Timing Control Hub™ for Next Gen P4™ processor
Recommended Application:
CK409 Compliant clock for Next Gen P4 Processor
Output Features:
• 2 - 0.7V current-mode differential CPU pairs
• 1 - 0.7V current-mode differential SRC pair
• 9 - PCI, 3 free running, 33MHz
• 3 - REF, 14.318MHz
• 3 - 3V66, 66.66MHz
• 1 - VCH/3V66, selectable 48MHz or 66MHz
• 2 - 48MHz
• 1 - 24/48MHz
Key Specifications:
• CPU/SRC outputs cycle-cycle jitter < 125ps
• 3V66 outputs cycle-cycle jitter < 250ps
• PCI outputs cycle-cycle jitter < 250ps
• +/- 300ppm frequency accuracy on CPU & SRC clocks
Features/Benefits:
• QuadRomTM frequency selection.
• Programmable output frequency.
• Programmable asynchronous 3V66&PCI frequency.
• Programmable output divider ratios.
• Programmable output rise/fall time.
• Programmable output skew.
• Programmable spread percentage for EMI control.
• Watchdog timer technology to reset system if system
malfunctions.
• Programmable watch dog safe frequency.
• Support I2C Index read/write and block read/write
operations.
• Uses external 14.318MHz reference input.
• Supports tight ppm accuracy clocks for Serial-ATA
• Supports spread spectrum modulation, 0 to -0.5%
down spread and +/- 0.25% center spread
• Supports CPU clks up to 400MHz
Functionality
Bit4 Bit3 Bit2 Bit1 Bit0
FS4 FS3 FS2 FS1 FS0
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
CPU
MHz
100.00
200.00
133.33
166.67
200.00
400.00
266.67
333.33
100.99
201.98
134.65
168.31
115.00
230.00
153.33
191.67
100.00
200.00
133.33
166.67
200.00
400.00
266.67
333.33
105.00
210.00
140.00
175.00
110.00
220.00
146.66
183.34
0734—07/16/04
AGP
MHz
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
67.33
67.33
67.33
67.32
76.66
76.66
76.66
76.66
66.66
66.66
66.66
71.43
66.66
66.66
66.66
66.66
69.99
69.99
69.99
69.99
73.33
73.33
73.33
73.33
PCI
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.66
33.66
33.66
33.66
38.33
38.33
38.33
38.33
33.33
33.33
33.33
35.71
33.33
33.33
33.33
33.33
35.00
35.00
35.00
35.00
36.66
36.66
36.66
36.66
Pin Configuration
*FS1/REF0
*FS0/REF1
REF2
VDDREF
X1
X2
GND
**FS2/PCICLK_F0
**FS4/PCICLK_F1
1
2
3
4
5
6
7
8
9
48 VDDA
47 GND
46 IREF
45 Reset#
44 GND
43 CPUCLKT1
42 CPUCLKC1
41 VDDCPU
40 CPUCLKT0
PCICLK_F2 10
VDDPCI 11
GND 12
^^PCICLK0 13
PCICLK1 14
PCICLK2 15
PCICLK3 16
VDDPCI 17
GND 18
PCICLK4 19
PCICLK5 20
**Sel24_48#/24_48MHz 21
**FS3/48MHz_0 22
48MHz_1 23
GND 24
39 CPUCLKC0
38 GND
37 SRCCLKT
36 SRCCLKC
35 VDD
34 VttPWR_GD/PD#
33 SDATA
32 SCLK
31 3V66_0
30 3V66_1
29 GND
28 VDD3V66
27 3V66_2
26 3V66_3/VCH
25 VDD48
* This pin have 120K pull-up to VDD
** This pin have 120K pull-down to GND
^^ An external 2.2K pull-down resistor is needed on this pin
48-pin SSOP
Note: FS1 and FS0 are equal to Intel CK409-defined FSA and FSB,
respectively.
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
1 page  
Integrated
Circuit
Systems, Inc.
Table1: QuadRom Frequency Selection Table (Continued)
Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
FS4 FS3 FS2 FS1 FS0
0100000
0100001
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
0101010
0101011
0101100
0101101
0101110
0101111
0110000
0110001
0110010
0110011
0110100
0110101
0110110
0110111
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
CPU
MHz
103.00
206.00
137.33
171.67
228.89
412.00
274.67
343.33
105.00
210.00
140.00
175.00
233.33
420.00
280.00
350.00
107.00
214.00
142.66
178.34
237.78
428.00
285.34
356.66
110.00
220.00
146.66
183.34
244.44
440.00
293.34
366.66
AGP
MHz
68.66
68.66
68.66
68.66
68.66
68.66
68.66
68.66
69.99
69.99
69.99
69.99
69.99
69.99
69.99
69.99
71.33
71.33
71.33
71.33
71.33
71.33
71.33
71.33
73.33
73.33
73.33
73.33
73.33
73.33
73.33
73.33
PCI
MHz
34.33
34.33
34.33
34.33
34.33
34.33
34.33
34.33
35.00
35.00
35.00
35.00
35.00
35.00
35.00
35.00
35.66
35.66
35.66
35.66
35.66
35.66
35.66
35.66
36.66
36.66
36.66
36.66
36.66
36.66
36.66
36.66
Spread
%
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
Table continued on next page.
ICS952607
Advance Information
0734—07/16/04
5
5 Page 
Integrated
Circuit
Systems, Inc.
ICS952607
Advance Information
I2C Table: Byte Count Register
Byte 8
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
Control
Function
Byte Count
Programming b(7:0)
Type
RW
RW
RW
RW
RW
RW
RW
RW
01
Writing to this register will configure how
many bytes will be read back, default is
0F = 15 bytes.
PWD
0
0
0
0
1
1
1
1
I2C Table: Watchdog Timer Register
Byte 9
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
WD7
WD6
WD5
WD4
WD3
WD2
WD1
WD0
Control
Function
WD Timer Bit 7
WD Timer Bit 6
WD Timer Bit 5
WD Timer Bit 4
WD Timer Bit 3
WD Timer Bit 2
WD Timer Bit 1
WD Timer Bit 0
Type
RW
RW
RW
RW
RW
RW
RW
RW
01
These bits represent X*290ms the
watchdog timer waits before it goes to
alarm mode. Default is 11 x 293ms =
3.2s.
PWD
0
0
0
0
1
0
1
1
I2C Table: VCO Control Select Bit & WD Timer Control Register
Byte 10
Pin #
Name
Control
Function
Type
Bit 7
-
M/NEN
M/N Programming
Enable
RW
Bit 6
-
WDEN
Watchdog Enable
R
Bit 5
-
WDFSEN
WD Safe Frequency
Mode
RW
Bit 4
-
WD SF4
RW
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
WD SF3
WD SF2
WD SF1
WD SF0
Watch Dog Safe Freq
Programming bits
RW
RW
RW
RW
0
Disable
Disable
Latched FS/Byte0
1
Enable
Enable
WD B10 b(4:0)
Writing to these bit will configure the safe
frequency as Byte0 bit (4:0).
PWD
0
1
0
0
0
0
0
0
I2C Table: VCO Frequency Control Register
Byte 11
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
N Div8
M Div6
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
Control
Function
N Divider Prog bit 8
M Divider
Programming bits
Type
RW
RW
RW
RW
RW
RW
RW
RW
01
The decimal representation of M and N
Divier in Byte 11 and 12 will configure the
VCO frequency. Default at power up =
latch-in or Byte 0 Rom table. VCO
Frequency = 14.318 x [NDiv(8:0)+8] /
[MDiv(6:0)+2]
PWD
X
X
X
X
X
X
X
X
0734—07/16/04
11
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet ICS952607.PDF ] | |
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