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PDF M32L1632512A Data sheet ( Hoja de datos )
| Número de pieza | M32L1632512A | |
| Descripción | 256K x 32-Bit x 2-Bank SGRAM | |
| Fabricantes | Elite Semiconductor | |
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ESMT et4U.comSGRAM
M32L1632512A
256K x 32 Bit x 2 Banks
Synchronous Graphic RAM
taSheFEATURES
ay JEDEC standard 3.3V power supply
.Dy LVTTL compatible with multiplexed address
wy Dual bank / Pulse RAS
wy MRS cycle with address key programs
w - CAS Latency ( 2, 3 )
GENERAL DESCRIPTION
The M32L1632512A is 16, 777, 216 bits synchro-
nous high data rate Dynamic RAM organized as 2 x
262, 144 words by 32 bits, fabricated with ESMT’s
high performance CMOS technology. Synchronous
- Burst Length ( 1, 2, 4, 8 & full page )
- Burst Type ( Sequential & Interleave )
my All inputs are sampled at the positive going
oedge of the system clock
y Burst Read Single-bit Write operation
.cy DQM 0-3 for byte masking
y Auto & self refresh
Uy 32ms refresh period (2K cycle)
y 100 pin QFP
design allows precise cycle control with the use of
system clock. I/O transactions are possible on every
clock cycle. Range of operating frequencies , progra-
mmable burst length, and programmable latencies
allows the same device to be useful for a variety of
high bandwidth, high performance memory system
applications.
Write per bit and 8 columns block write improves
performance in graphic systems.
et4Graphic Features
ey SMRS cycle
h- Load mask register
- Load color register
Sy Write Per Bit
www.Datay Block Write (8 Columns)
ORDERING INFORMATION
Part NO.
M32L1632512A-5Q
Cycle Clock
Access tRDL
time Frequency time@CL=3 (clk)
5ns 200MHz
4.5ns
1
M32L1632512A-5SQ 5ns 200MHz
4.5ns
2
M32L1632512A-6Q 6ns 166MHz
5.5ns
1
M32L1632512A-6SQ 6ns 166MHz
5.5ns
2
M32L1632512A-7Q 7ns 143MHz
6.0ns
1
Elite Semiconductor Memory Technology Inc.
M32L1632512A-7SQ 7ns
.comM32L1632512A-8Q 8ns
UM32L1632512A-8SQ 8ns
143MHz
125MHz
125MHz
6.0ns
6.5ns
6.5ns
2
1
2
w.DataSheet4Publication Date : Jun. 2001
ww Revision : 1.6
1/54
1 page  
ESMT
M32L1632512A
DC CHARACTERISTICS
Recommended operating condition unless otherwise noted, TA = 0 to 70 °C VIH(min) /VIL(max) =2.0V/0.8V
Parameter
Operating Current
(One Bank Active)
Symbol
Test Condition
Burst Length = 1
ICC1 tRC ≥ tRC(min), tCC ≥ tCC(min)
IOL = 0 mA
CAS
Version
Unit Note
Latency -5/5S -6/6S -7/7S -8/8S
3 230 210 195 170 mA 1
2 230 210 195 170
Precharge Standby Current ICC2P CKE ≤ VIL(max), tCC = 15ns
222 2
mA
in power-down mode
tICC2PS CKE ≤ VIL(max), CLK ≤ VIL(max), CC = ∞ 2 2 2 2
tICC2N CKE ≥ VIH(min), CS ≥ VIH(min), CC = 15ns 35 35 35 35
Precharge Standby Current
in non power-down mode
Input signals are changed one time during
30ns
mA
tICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), CC = ∞
input signals are stable
15 15 15 15
Active Standby Current
in power-down mode
ICC3P CKE ≤ VIL(max), tCC = 15ns
tICC3PS CKE ≤ VIL(min), CLK ≤ VIL(max), CC = ∞
333
333
3
mA
3
Active Standby Current
tICC3N CKE ≥ VIH(min), CS ≥ VIH(min), CC = 15ns 60 60 60 60
in non power-down mode
Input signals are changed one time during
mA
(One Bank Active)
30ns
tICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), CC = ∞
input signals are stable
20 20 20 20
Operating Current
(Burst Mode)
IOL = 0 mA, Page Burst
ICC4 All Banks Activated, tCCD = tCCD
(min)
3
2
230 210 195 170
mA 1, 2
230 210 195 170
Refresh Current
ICC5
Self Refresh Current
Operating Current
(One Bank Block Write)
ICC6
ICC7
tRC ≥ tRC(min)
3
2
CKE ≤ 0.2V
tCC ≥ tCC(min), IOL = 0 mA, tBWC(min)
190 170 160 150
mA
190 170 160 150
2 2 2 2 mA
220 200 190 180 mA
3
4
*Note : 1. Measured with outputs open.
2. Assumes minimum column address update cycle tCCD(min).
3. Refresh period is 32ms.
4. Assumes minimum column address update cycle tBWC(min).
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6
5/54
5 Page 
ESMT
M32L1632512A
Test Mode
A8 A7
Type
A6
0 0 Mode Register Set 0
01
Vendor
0
1 0 Use 0
11
Only
0
Write Burst Length
1
A9 Length
1
0 Burst 1
1 Single Bit 1
CAS Latency
A5 A4 Latency
0 0 Reserved
01
-
10
2
11
3
0 0 Reserved
0 1 Reserved
1 0 Reserved
1 1 Reserved
Burst Type
A3 Type
0 Sequential
1 Interleave
A2
0
0
0
0
1
1
1
1
Burst Length
A1 A0 BT = 0 BT = 1
00
1 Reserved
01
2 Reserved
10
4
4
11
8
8
0 0 Reserved Reserved
0 1 Reserved Reserved
1 0 Reserved Reserved
1 1 256(Full) Reserved
(Note 3)
Special Mode Register Programmed with SMRS
Address A10
A9
A8
A7
A6
Function
X
LC
A5
LM
A4
A3 A2
X
A1 A0
POWER UP SEQUENCE
Load Color
A6 Function
0 Disable
1 Enable
Load Mask
A5 Function
0 Disable
1 Enable
(Note 4)
1.Apply power and start clock, Attempt to maintain CKE = ”H”, DQM = ”H” and the other pin are NOP
condition at the inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200 µ s.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 may be changed.
The device is now ready for normal operation.
Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.
2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.
3. The full column burst (256bit) is available only at Sequential mode of burst type.
4. If LC and LM both high (1), data of mask and color register will be unknown.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6
11/54
11 Page | ||
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