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Intel - Extended Temperature PCISET System Controller

Numéro de référence FW82439TX
Description Extended Temperature PCISET System Controller
Fabricant Intel 
Logo Intel 





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FW82439TX fiche technique
PRELIMINARY
et4IUnt.ecl8oE2mx4t3e9nTdXedSyTseDtmeamptaesCrhaoetnuetrtreol4le3r0T(MXTPXCCI)SET:n Supports Mobile and Desktop
en Supports the Pentium® Processor
hFamily Host Bus at 66 MHz and 60 MHz
Sat 3.3V and 2.5V
tan PCI 2.1 Compliant
a n Integrated Data Path
.D n Integrated DRAM Controller
4 Mbytes to 256 MBytes main
w memory
w 64-Mbit DRAM/SDRAM Technology
w Support
FPM (Fast Page Mode), EDO and
mSDRAM DRAM Support
6 RAS Lines Available
oIntegrated Programmable Strength
for DRAM Interface
.cCAS-Before-RAS Refresh, Extended
Refresh and Self Refresh for EDO
CAS-Before-RAS and Self Refresh
Ufor SDRAM
n Integrated L2 Cache Controller
t464-MB DRAM Cacheability
Direct Mapped Organization—Write
Back Only
eSupports 256K and 512K Pipelined
Burst SRAM and DRAM Cache
eSRAM
Cache Hit Read/Write Cycle Timings
hat 3-1-1-1
Back-to-Back Read/Write Cycles at
S3-1-1-1-1-1-1-1
64K x 32 SRAM also supported
n Fully Synchronous, Minimum Latency
30/33-MHz PCI Bus Interface
Five PCI Bus Masters (including
PIIX4)
10 DWord PCI-to-DRAM Read
Prefetch Buffer
18 DWord PCI-DRAM Post Buffer
Multi-Transaction Timer to Support
Multiple Short PCI Transactions
n Power Management Features
PCI CLKRUN# Support
Dynamic Stop Clock Support
Suspend to RAM (STR)
Suspend to Disk (STD)
Power On Suspend (POS)
Internal Clock Control
SDRAM and EDO Self Refresh
During Suspend
ACPI Support
Compatible SMRAM (C_SMRAM)
and Extended SMRAM (E_SMRAM)
SMM Writeback Cacheable in
E_SMRAM Mode up to 1 MB
3.3/5V DRAM, 3.3/5V PCI 3.3/5V Tag
and 3.3/2.5 SRAM Support
n Test Features
NAND Tree Support for all Pins
n Supports the Universal Serial Bus
(USB)
n 324-Pin MBGA 430TX PCIset Xcelerated
Controller (MTXC) with integrated Data
Paths
taThe Intel 430TX PCIset (430TX) consists of the 82439TX System Controller (MTXC) and the 82371AB PCI
aISA IDE Xcelerator (PIIX4). The 430TX supports both mobile and desktop architectures. The 430TX forms a
Host-to-PCI bridge and provides the second level cache control and a full function 64-bit data path to main
memory. The MTXC integrates the cache and main memory DRAM control functions and provides bus
.Dcontrol to transfers between the CPU, cache, main memory, and the PCI Bus. The second level (L2) cache
controller supports a writeback cache policy for cache sizes of 256 Kbytes and 512 Kbytes. Cacheless
designs are also supported. The cache memory can be implemented with pipelined burst SRAMs or DRAM
cache SRAMs. An external Tag RAM is used for the address tag and an internal Tag RAM for the cache line
wstatus bits. For the MTXC DRAM controller, six rows are supported for up to 256 Mbytes of main memory.
The MTXC is highly integrated by including the Data Path into the same BGA chip. Using the snoop ahead
feature, the MTXC allows PCI masters to achieve full PCI bandwidth. For increased system performance, the
wMTXC integrates posted write and read prefetch buffers. The 430TX integrates many Power Management
features that enable the system to save power when the system resources become idle.
mInformation in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is
w ogranted by this document or by the sale of Intel products. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a
.cparticular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. The Intel 430TX
PCIset may contain design defects or errors known as errata. Current characterized errata are available on request. Third-party brands and names are the property of
their respective owners.
www.DataSheet4U© INTEL CORPORATION 1999
February 1999
Order Number: 273234-001

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