PDF HY27UG082G2M Data sheet ( Hoja de datos )

Número de pieza	HY27UG082G2M
Descripción	(HY27xx Series) 2G-Bit NAND Flash
Fabricantes	Hynix Semiconductor
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No Preview Available ! m Preliminary o HY27UG(08/16)2G2M Series .c HY27SG(08/16)2G2M Series t4U 2Gbit (256Mx8bit / 128Mx16bit) NAND Flash eeDocument Title Sh2Gbit (256Mx8bit / 128Mx16bit) NAND Flash Memory .DataRevision History wwRevision w No. History Draft Date Remark 0.0 Initial Draft. Nov. 19. 2004 Preliminary m1) Add Errata oSpecification .cRelaxed value tCLS 0 5 tCLH tWP tALS tALH tDS tWC tR 10 25 0 10 20 50 25us 15 45 5 15 25 70 27us UCase tRC tRP tREH tREA t4Specification Read(all) 50 20 20 30 Except for Relaxed value ID Read 50 20 20 30 e0.1 ID Read 60 25 30 30 Jan. 20. 2005 Preliminary he2) Add note.4(table14) 3) Add application note(Power on/off Sequence & Auto sleep mode) S- Texts & figures are added. 4) Change AC parameters taCase tDH Before x8, x16 10 .DaAfter x8 10 x16 15 1) Change AC parameters wwBefore case x8 x16 tDH 10 15 w0.2 Afer x8, x16 15 Mar. 03. 2005 Preliminary 2) Add tADL(=100ns) parameters m3) Add Muliti Die Concurrent Operations and Extended Read Status .co- Texts and table are added. 4) Edit Table.8 t4U5) Change FBGA Package Dimension www.DataSheeRev 0.2 / Mar. 2005 1 1 page Preliminary HY27UG(08/16)2G2M Series HY27SG(08/16)2G2M Series 2Gbit (256Mx8bit / 128Mx16bit) NAND Flash 1& 1& 1& 1& 1& 1& 5% 5( &( 1& 1& 9FF 9VV 1& 1& &/( $/( :( :3 1& 1& 1& 1& 1& 1$1')ODVK 7623 [ 1& 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 35( 9FF 9VV 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 5% 5( &( 1& 1& 9FF 9VV 1& 1& &/( $/( :( :3 1& 1& 1& 1& 1& 1$1')ODVK 7623 [ 9VV ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 1& 35( 9FF 1& 1& 1& ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 9VV Figure 2. 48TSOP1 Contactions, x8 and x16 Device 1& 1& 1& 1& 1& 1& 5% 5( &( 1& 1& 9FF 9VV 1& 1& &/( $/( :( :3 1& 1& 1& 1& 1& 1$1')ODVK :623 [ 1& 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 35( 9FF 9VV 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 5% 5( &( 1& 1& 9FF 9VV 1& 1& &/( $/( :( :3 1& 1& 1& 1& 1& 1$1')ODVK :623 [ 9VV ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 1& 35( 9FF 1& 1& 1& ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 9VV Figure 3. 48WSOP1 Contactions, x8 and x16 Device Rev 0.2 / Mar. 2005 5 5 Page Preliminary HY27UG(08/16)2G2M Series HY27SG(08/16)2G2M Series 2Gbit (256Mx8bit / 128Mx16bit) NAND Flash 3. DEVICE OPERATION 3.1 Page Read. Upon initial device power up, the device defaults to Read mode. This operation is also initiated by writing 00h and 30h to the command register along with four address cycles. In two consecutive read operations, the second one doesn’t’ need 00h command, which four address cycles and 30h command initiates that operation. Two types of operations are available : random read, serial page read. The random read mode is enabled when the page address is changed. The 2112 bytes (X8 device) or 1056 words (X16 device) of data within the selected page are transferred to the data regis- ters in less than 25us(tR). The system controller may detect the completion of this data transfer (tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read out in 50ns cycle time by sequentially pulsing RE#. The repetitive high to low transitions of the RE# clock make the device output the data starting from the selected column address up to the last column address. The device may output random data in a page instead of the consecutive sequential data by writing random data out- put command. The column address of next data, which is going to be out, may be changed to the address which follows random data output command. Random data output can be operated multiple times regardless of how many times it is done in a page. 3.2 Page Program. The device is programmed basically by page, but it does allow multiple partial page programming of a word or consec- utive bytes up to 2112 (X8 device) or words up to 1056 (X16 device), in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 4 times for main array (X8 device:1time/512byte, X16 device:1time/256word) and 4 times for spare array (X8 device:1time/16byte ,X16 device:1time/8word). The addressing should be done in sequential order in a block. A page program cycle consists of a serial data loading period in which up to 2112bytes (X8 device) or 1056words (X16 device) of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the four cycle address inputs and then serial data. The words other than those to be programmed do not need to be loaded. The device supports random data input in a page. The column address of next data, which will be entered, may be changed to the address which follows random data input command (85h). Random data input may be operated multi- ple times regardless of how many times it is done in a page. The Page Program confirm command (10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write state controller automatically exe- cutes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the RB# output, or the Status bit (I/ O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit (I/O 0) may be checked. The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Sta- tus command mode until another valid command is written to the command register. Figure 15 details the sequence. Rev 0.2 / Mar. 2005 11 11 Page

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