Z80380 Datasheet PDF - Zilog
| Part Number | Z80380 | |
| Description | Microprocessor | |
| Manufacturers | Zilog | |
| Logo |  |
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ZILOG
MICROPROCESSOR
m PRODUCT SPECIFICATION
ataSheet4U.co Z380FEATURES
.Ds Static CMOS Design with Low-Power Standby Mode
wOption
wws 32-Bit Internal Data Paths and ALU
ms Operating Frequency
o- DC-to-18 MHz at 5V
.c- DC-to-10 MHz at 3.3V
s Enhanced Instruction Set that Maintains Object-Code
UCompatibility with Z80® and Z180™ Microprocessors
t4s 16-Bit (64K) or 32-Bit (4G) Linear Address Space
es 16-Bit Data Bus with Dynamic Sizing
™
MICROPROCESSOR
s Two-Clock Cycle Instruction Execution Minimum
s Four Banks of On-Chip Register Files
s Enhanced Interrupt Capabilities, Including
16-Bit Vector
s Undefined Opcode Trap for Z380™ Instruction Set
s On-Chip I/O Functions:
- Six-Memory Chip Selects with Programmable Waits
- Programmable I/O Waits
- DRAM Refresh Controller
s 100-Pin QFP Package
heGENERAL DESCRIPTION
SThe Z380™ Microprocessor is an integrated high-
taperformance microprocessor with fast andefficientthrough-
put and increased memory addressing capabilities. The
aZ380™ offers a continuing growth path for present Z80-or
Z180-based designs, while maintaining Z80® CPU and
Z180® MPU object-code compatibility. The Z380™ MPU
.Denhancements include an improved 280 CPU, expanded
4-Gbyte space and flexible bus interface timing.
wAn enhanced version of the Z80 CPU is key to the Z380
MPU. The basic addressing modes of the Z80 micropro-
wcessor have been augmented as follows: Stack Pointer
mRelative loads and stores, 16-bit and 24-bit indexed off-
w osets, and more flexible Indirect Register addressing, with
www.DataSheet4U.call of the addressing modes allowing access to the entire
32-bit address space. Additions made to the instruction
set, include a full complement of 16-bit arithmetic and
logical operations, 16-bit I/O operations, multiply and
divide, plus a complete set of register-to-register loads
and exchanges.
The expanded basic register file of the Z80 MPU micropro-
cessor includes alternate register versions of the IX and IY
registers. There are four sets of this basic Z80 micropro-
cessor register file present in the Z380 MPU, along with the
necessary resources to manage switching between the
different register sets. All of the register-pairs and index
registers in the basic Z80 microprocessor register file are
expanded to 32 bits.
PS010001-0301
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ZILOG
MICROPROCESSOR
/M1 Machine Cycle One (output, active Low, tri-state). This
signal is active during interrupt acknowledge and RETI
transactions.
/IORD Input, Output Read Strobe (output, active Low, tri-
state). This signal is used strobe data from the peripherals
during I/O read transactions. In addition, /IORD is active
during the special RETI transaction and the I/O heartbeat
cycle in the Z80 protocol case.
/IOWR Input/Output Write Strobe (output, active Low, tri-
state). This signal is used to strobe data into the peripher-
als during I/O write transactions.
/LMCS Low Memory Chip Select (output, active Low, tri-
state). This signal is activated during a memory read or
memory write transaction when accessing the lower por-
tion of the linear address space within the first 16 Mbytes,
but only if this chip select function is enabled.
/MCS3-/MCS0 Mid-range Memory Chip Selects (output,
active Low, tri-state). These signals are individually active
during memory read or write transactions when accessing
themid-range portionsofthe linear addressspace within the
first 16 Mbytes. These signals can be individually enabled
or disabled.
/MRD Memory Read (output, active Low, tri-state). This
signal indicates thatthe addressed memory location should
place its data on the data bus as specified by the /BHEN
and /BLEN control signals. /MRD is active from the end of
T1 until the end of T4 during memory read transactions.
/MSIZE Memory Size (input, active Low). This input, from
the addressed memory location, indicates if it is word size
(logic High) or byte size (logic Low). In the latter case, the
addressed memory should be connected to the D15-D8
portion of the data bus, and an additional memory transac-
tion will automatically be generated to complete a word
size data transfer.
/MWR Memory Write (output, active Low, tri-state). This
signal indicates thatthe addressed memory location should
store the data on the data bus, as specified by the /BHEN
and /BLEN control signals. /MWR is active from the end of
T2 until the end of T4 during memory write transactions.
/RESET Reset (input, active Low). This input must be
active for a minimum of five BUSCLK periods to initialize
the Z380 MPU. The effect of /RESET is described in detail
in the Reset section.
/TREFA Timing Reference A (output, active Low, tri-state).
This timing reference signal goes Low at the end of T2 and
returns High at the end of T4 during a memory read,
memory write or refresh transaction. It can be used to
control the address multiplexer for a DRAM interface or as
the /RAS signal at higher processor clock rates.
/TREFC Timing Reference C (output, active Low, tri-state).
This timing reference signal goes Low at the end of T3 and
returns High at the end of T4 during a memory read,
memory write or refresh transaction. It can be used as the
/CAS signal for DRAM accesses.
/TREFR Timing Reference R (output, active Low, tri-state).
This timing reference signal goes Low at the end of T1 and
returns High at the end of T4 during a memory read,
memory write or refresh transaction. It can be used as the
/RAS signal for DRAM accesses.
/UMCS Upper Memory Chip Select (output, active Low, tri-
state). This signal is activated during a memory read,
memory write, or optionally a refresh transaction when
accessing the highest portion of the linear address space
within the first 16 Mbytes, but only if this chip select
function is enabled.
VDD Power Supply. These eight pins carry power to the
device. They must be tied to the same voltage externally.
VSS Ground. These eight pins are the ground references for
the device. They must be tied to the same voltage exter-
nally.
/WAIT Wait (input, active Low). This input is sampled by
BUSCLK or IOCLK, as appropriate, to insert Wait states
into the current bus transaction.
The conditioning and characteristics of the Z380 MPU pins
under various operation modes are defined in Table 1.
/NMI Nonmaskable Interrupt(input, falling edge-triggered).
This input has higher priority than the maskable interrupt
inputs /INT3-INT0.
PS010001-0301
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| Information | Total 70 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ Z80380.PDF Datasheet ] | |
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