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PDF ICS2002 Data sheet ( Hoja de datos )
| Número de pieza | ICS2002 | |
| Descripción | Wavedec Digital Audio Codec | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS2002
Wavedec™ Digital Audio Codec
Description
The ICS2002 is a mixed-signal integrated circuit providing a
low-cost recording and playback solution for multimedia audio
applications. These applications include document annotation,
voice mail, interactive games, multimedia sound record/play-
back, and Windows™ sound production. The ICS2002 sup-
ports the record and playback of 16-bit audio data, and provides
a 8/16-bit parallel interface to the industry standard PC bus.
Features
• Digital audio 8/16-bit record/playback
• Fully programmable sample rates including industry
standards:
- 44.1 kHz
- 22.050 kHz
- 11.025 kHz
- 8.00 kHz
- 5.513 kHz
• DAC output oversampled to simplify external filtering.
• Four data formats:
- 16 bit linear
- 8 bit linear
- 8 bit u-law
- 8 bit a-law
• 16 step analog output level control, -1.5dB/step
• 8-bit log scale digital volume control
• Oversampling ADC with input filter.
• Programmable IIR filters for input anti-aliasing and output
reconstruction.
• ISA bus interface
• 8/16-bit DMA and I/O transfer modes
• Input/output FIFO buffer
• Power-down mode
• 44-pin PLCC package
Block Diagram
ICS2002RevF093094
Wavedec is a trademark of Integrated Circuit Systems, Inc.
1 page  
ICS2002
Electrical Characteristics
VDD = 5.0V ± 10%; GND =0V; TA = 0°C to +70°C
AC/DYNAMIC
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Address setup to command
tAS 10
ns
Address hold from command
tAH 10
ns
Command cycle time
tCCY
100
ns
Address valid to /IOCS16 delay
tAID
50 ns
IOCS16 hold from address invalid
tIH 0
ns
Data valid to /IOW
tDS 50
ns
/IOR active to valid data
tDAC
60 ns
Data hold after /IOR
tDHR
0
ns
Data hold after /IOW
tDHW
10
ns
/DACK setup to /IOR
tDAR
30
ns
/DACK setup to /IOW
tDAW
50
ns
/DACK hold from command
tDAH
50
ns
/CS setup to command
tCS 10
ns
/CS hold from command
tCH 10
ns
TC setup to command inactive
tTS 25
ns
TC hold from command
tTH 0
ns
5
5 Page 
ICS2002
Indirect Register Definitions
All writeable bits/registers are also readable. In addition, there
are some read only bits/registers, which are noted where appro-
priate.
Reserved bits should be written to zero, and read back zeros.
Reserved registers should not be written or read.
Except where noted, registers should be accessed as 8 bit
registers via address BASE+2.
General Purpose Registers
IR4E Register Access Mode Select
This register must be written to 01h for any other
indirect (or direct) accesses to occur, except for RA
writes, which always occur based on chip select. This
indirect address allows multiple companion chips to
share resources in a system (such as bus buffers, address
decodes, interrupts, and DMA channels).
This register is cleared only by hardware reset, and in
unaffected by MCR (see below).
IR80 Chip Control
Bits 7:3 - reserved
Bit 2 - Sound Source Emulation Mode (SSMODE)
This bit sets the chip to operate in Sound Source Emu-
lation mode. In Sound Source Emulation Mode, the two
address pins (SA1, SA0) are mapped to match the PC
parallel port as used by the Sound Source as follows:
Bit 1 - Chip STAND ALONE Mode
This bit sets the chip to operate in STAND ALONE
mode. In STAND ALONE mode, the STATUS and RA
registers are accessible at BASE+0 and BASE+1. This
mode should be used to speed register access when the
ICS2002 is being used by itself, without other ICS
chips sharing resources (such as address decodes, inter-
rupts, DMA channels, bus buffers, etc.).
When bit 1 is zero, the ICS2002 will operate in COM-
PANION mode. In this mode, the STATUS register is
mapped only to indirect address 83h. This is done to
avoid conflict with other ICS chips that will provide
STATUS and RA read back at the first two base ad-
dresses.
In addition, STAND ALONE mode configures the
DRQP, DRQR, and IRQ pins to operate as outputs, with
both one and zero levels being actively driven. When
in COMPANION mode, these pins have a strong source
for the high state and a weak sink for the low state to
allow wire-and connections to other ICS chips.
This bit is reset by hardware reset only, not by MCR.
Bit 0 - Master Chip Reset (MCR)
0 - Hold chip in reset
1 - Remove reset
This bit is cleared to zero by a hardware reset. Thus, any
functions reset by MCR are also reset by the RESET
pin.
Chip Address
0
1
2
3
Sound Source
Data
Status
Control
unused
IC2002
DH
Status
DL
RA
To use this mode, the chip must be configured before
the Sound Source compatible application is run (I/O
Mode DMA, DSP loaded and running, SR running,
etc.). Then, the IC2002 is put in SSMODE and RA
(now at address 3) is written to 8Bh. In the PC, the BIOS
pointer to the parallel port is changed to the base address
of the IC2002 chip, and the application can then be
started.
This bit is reset by MCR. Hence, it must be set after
MCR is set, on a second write to this register.
11
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet ICS2002.PDF ] | |
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