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PDF ICS2008B Data sheet ( Hoja de datos )
| Número de pieza | ICS2008B | |
| Descripción | SMPTE Time Code Receiver/Generator | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
ICS2008B
SMPTE Time Code Receiver/Generator
General Description
The ICS2008B, SMPTE Time Code Receiver / Generator
chip, is a VLSI device designed in a low power CMOS
process. This device provides the timing coordination for
Multimedia sight and sound events. Although it is aimed at
a PC Multimedia environment, the ICS2008B is easily
integrated into products requiring SMPTE time code
generation and/or reception in LTC (Longitudinal Time
Code) and/or VITC (Vertical Interval Time Code) formats
and MTC (MIDI Time Code) translation.
Taking its input from composite video, S-Video, or an
audio track, the ICS2008B can read SMPTE time code in
VITC and LTC formats. Time code output formats are LTC
and VITC. All are available simultaneously. A UART is
provided for the user to support MTC or tape transport
control.
The processor interface is compatible with the IBM PC and
ISA bus compatible computers and is easily interfaced to
other processors and micro-controllers.
The ICS2008B is an improved version of the ICS2008,
with additional features and capabilities.
ICS2008 ICS2008B 2008 2008B
Block Diagram
Features
• Meets SMPTE VITC Specifications
• Meets SMPTE and EBU LTC Specifications
• Time Code Burn-in Window
– Programmable position, size and character attributes
• LTC edge rate control
– Conforms to EBU Tr and Tf Specifications
• Internal and external sync sources
– Genlock to video or house sync inputs
– Improved video timing lock during VCR pause and
shuttle modes
– Internally generated timing from oscillator input
– External click input
– Internal Timer
Allows 1/4 Frame MIDI Time Code Messages
• LTC and VITC Generators
– Real Time SMPTE Rates:
30Hz, 29.97Hz, 25Hz, 24Hz
– Time Code Modes
Drop Frame and Color Frame
– VITC can be inserted on two lines from 10-40
(SMPTE specifies lines 10-20)
– Jam Sync, freewheeling, error bypass/correction,
and plus-one-frame capability
• LTC Receiver
– Synchronize bit rates from 1/30th nominal to 80X
nominal playback speed.
• VITC Receiver
– Reads code from any or all selected scan lines.
– VITC search mode, will search through VBI lines until
VITC is found.
• New UART frequency of 38.4 K for tape transport control
ICS2008B Rev D 4/05/05
ICS reserves the right to make changes in the device data identified in this publication without
further notice. ICS advises its customers to obtain the latest version of all device data to verify
that any information being relied upon by the customer is current and accurate.
1 page  
ICS2008B
UART
A general purpose UART is provided for MIDI, video trans-
port control, etc. Most serial interface transport controls use
9600 and 38.4K BAUD. The CTS and RTS modem controls are
needed in these applications. MIDI ports use 31.25K BAUD,
but they do not require modem controls. The receiver includes
a four byte FIFO to reduce the real time interrupt servicing re-
quirements. This is particularly important in MIDI applications
because of the high data rate and the fact that many MIDI mes-
sages are three bytes long. The transmitter is doubled
buffered. Interrupts can be generated on both
receiver data available and/or transmit buffer empty.
Interrupt Timer
The interrupt timer is a general purpose 10 bit timer with three
clock sources (100 kHz, the LTC receive clock and the LTC
transmit clock). Although the timer is general purpose in
nature, its main purpose is to facilitate the timed generation of
MIDI time code messages.
Processor Interface
The ICS2008B supports standard microprocessor interfaces
and busses, such as the PC bus, to allow access to six control/
status and data registers. These six registers are organized into
two groups, one set of four for SMPTE control and the other
set of two for direct UART port control. Each set of registers is
selected with its own chip select, SMPTECS* and UARTCS.*
SMPTE Registers
The SMPTE register set allows access to four direct and
64 indirect registers. The first two direct access registers
addressed at locations 0 and 1 are for status and interrupt con-
trol. The 64 indirect registers are accessed by writing an
indirect address into SMPTE2 and reading from or writing to
SMPTE3. If the AUTOINC bit in SMPTE2 is set to 1, the
indirect register address is automatically incremented after an
access to SMPTE3. This eases the task of reading or writing
sequential indirect locations.
SM PTECS*
0
0
0
0
A1
0
0
1
1
A 0 R E G IS TE R
0 SM PTE0 -InterruptC ontrol/Status
1 SM PTE1 -SM PTE Status
0 SM PTE2 -IndirectAddress R egister
1 SM PTE3 -IndirectR egisterD ata
The SMPTE0 Register contains the SMPTE interrupt controls
and status and the VITC read status. The four interrupt bits,
LRI, LXI, VLI and TMI reflect the status of the potential
interrupt sources to the processor. When a bit is set to one and
the corresponding enable bit, LRIEN, LXIEN or VLIEN, is also
set, the INTR output will be activated. Interrupts are cleared by
reading SMPTE0.
76543210
SMPTE0
Interrupt Control/Status
LRI (LTC RCV Interrupt)
LXI (LTC XMT Interrupt)
VLI (Video Line Interrupt)
LRIEN (1-enable, 0-disable)
LXIEN (1-enable, 0-disable)
VLIEN (1-enable, 0-disable)
TMI (Timer Interrupt)
TMIEN (1-enable, 0-disable)
LRI — This bit indicates that a LTC receive interrupt has
occurred. In order for an actual processor interrupt to occur,
the LRIEN bit must also be set. An LRI interrupt occurs upon
reception of the last byte of LTC receive data which was pre-
ceded by a valid LTC SYNC pattern. That is after the 64th
LTC receive bit time in the forward direction. At normal
frame rates, if the LTC transmitter is synchronized with the
LTC receiver, there is about 3 milliseconds after this interrupt
before the LTC transmit data for the next output frame is
transferred to the output buffer.
LXI — This bit indicates that a LTC transmit interrupt has
occurred. When this bit is set, and the corresponding LXIEN
bit has been set, the INTR output will be activated. The LTC
transmit interrupt is activated after the transfer of LTC trans-
mit data to the output buffer. This occurs after LTXEN is set to
one and after the 72nd LTC transmits bit time of the current
frame, “N.” Data loaded after this interrupt will appear in out-
put frame “N+2” since the transmitter is double buffered.
VLI — This is a status bit that indicates that the video line
selected via the Video Interrupt Line Register, VR9, has
passed. When the VLIEN bit is also set, the processor will be
interrupted. This interrupt can be used by the processor to
determine when to sample the VITC time code when time
locked to a video source. It will also be used to facilitate
detection of LTC time code dropout and off speed LTC code,
e.g. shuttling operations.
TMI — This bit indicates that a timer interrupt has occurred.
When the TMIEN bit is also set to a one, the INTR output will
be activated. This interrupt is intended to facilitate timing
MIDI clocks and MIDI Quarter Frame messages.
5 ICS2008B Rev D 4/05/05
5 Page 
ICS2008B
Indirect Register Map
76543210
LTC 00
BINARY GROUP 1
FRAME UNITS
Read 01
BINARY GROUP 2
COLR FRAME DROP FRAME
FRAMES TENS
02 BINARY GROUP 3
SECONDS UNITS
03
BINARY GROUP 4
PHASE CORR
SECONDS TENS
04 BINARY GROUP 5
MINUTES UNITS
05
BINARY GROUP 6
BG FLAG 55
MINUTES TENS
06 BINARY GROUP 7
HOURS UNITS
07
BINARY GROUP 8
BG FLAG 75 UNASSIGNED
HOURS TENS
LTC 08
Write . . .
SAME BIT DEFINITION AS LTC READ BUFFER
OF
VITC
10
BINARY GROUP 1
FRAME UNITS
READ1 11
BINARY GROUP 2
COLR FRAME DROP FRAME
FRAMES TENS
12 BINARY GROUP 3
SECONDS UNITS
13
BINARY GROUP 4
FIELD MARK
SECONDS TENS
14 BINARY GROUP 5
MINUTES UNITS
15
BINARY GROUP 6
BG FLAG 55
MINUTES TENS
16 BINARY GROUP 7
HOURS UNITS
17
BINARY GROUP 8
BG FLAG 75 UNASSIGNED
HOURS TENS
VITC
18
Read2 . . .
SAME BIT DEFINITION AS VITC READ1 BUFFER
1F
VITC
20
Write . . .
SAME BIT DEFINITION AS VITC READ1 BUFFER
27
Regs 28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - BURN-IN WINDOW COLUMN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - BURN-IN WINDOW LINE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2A - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
FRAMES
----------------------------------
2B - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
SECONDS
----------------------------------
2C - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MINUTES
----------------------------------
2D - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
HOURS
----------------------------------
2E VITC1WE
0
0 -----------
VITC WRITE LINE 1
-----------
2F VITC2WE
0
0 -----------
VITC WRITE LINE 2
-----------
30 VITC1RE NOCODE1 CRCERR1 - - - - - - - - - - -
VITC READ LINE 1
-----------
31 VITC2RE NOCODE2 CRCERR2 - - - - - - - - - - -
VITC READ LINE 2
-----------
32 PAL
VID2_S
VID1_S
VOUTSEL
VITCSEL VSYNCSEL
VTRES
GEN_EN
33 0
0 - - - - - - - - - - - - - - - - - - - - - - VIDEO LINE INTERRUPT (LINE#) - - - - - - - - - - - - - - - - -
34 LTCOUTSEL - - - - LTCSYNCSEL - - - -
LTXEN
LXCLKSEL
0
LTXFREE EDGE RATE
35 0 0 0
- - - - - - - - - - - - - - - - - - LTC GAIN - - - - - - - - - - - - - - - - -
36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - FRAME RATE (low byte, write only) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
37 0 0 0 0 - - - - - - - FRAME RATE (high byte, write only) - - - - - - -
38 reserved
39 reserved
3A reserved
3B reserved
3C - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TIMER VALUE (low byte, write only) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
3D RUN
CLKSEL
0 0 0 TIMER VALUE (high)
3E 0
0
0
HSF
WIN_SIZE
WINDOW ATTRIBUTE
BLINK
3F - - - - - - - - - - - - - - - SOFT LTC SYNC (write only, no data) - - - - - - - - - - - - - - - -
11 ICS2008B Rev D 4/05/05
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet ICS2008B.PDF ] | |
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