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PDF IDT72V70210 Data sheet ( Hoja de datos )
| Número de pieza | IDT72V70210 | |
| Descripción | 3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 1024 x 1024 | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH
1,024 x 1,024
IDT72V70210
FEATURES:
• 32 serial input and output streams
• 1,024 x 1,024 channel non-blocking switching at 2.048 Mb/s
• Per-channel Variable Delay Mode for low-latency applications
• Per-channel Constant Delay Mode for frame integrity applications
• Automatic identification of ST-BUS® and GCI serial streams
• Automatic frame offset delay measurement
• Per-stream frame delay offset programming
• Per-channel high impedance output control
• Per-channel processor mode to allow microprocessor writes to
TX streams
• Direct microprocessor access to all internal memories
• Memory block programming for quick set-up
• IEEE-1149.1 (JTAG) Test Port
• Internal Loopback for testing
•· Available in 144-pin Ball Grid Array (BGA) and 144-pin Thin Quad
Flatpack (TQFP) packages
• Operating Temperature Range -40°C to +85°C
• 3.3V I/O with 5V tolerant inputs and TTL compatible outputs
DESCRIPTION:
The IDT72V70210 has a non-blocking switch capacity of 1,024 x 1,024
channels at 2.048 Mb/s. With 32 inputs and 32 outputs, programmable per
stream control, and a variety of operating modes the IDT72V70210 is designed
for the TDM time slot interchange function in either voice or data applications.
Some of the main features of the IDT72V70210 are low power 3.3 Volt
operation, automatic ST-BUS®/GCI sensing, memory block programming,
simple microprocessor interface, one cycle direct internal memory accesses,
JTAG Test Access Port (TAP) and per stream programmable input offset delay,
variable or constant throughput modes, internal loopback, output enable, and
Processor Mode.
FUNCTIONAL BLOCK DIAGRAM
Vcc GND RESET
TMS TDI TDO TCK TRST
ODE
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
RX8
RX9
RX10
RX11
RX12
RX13
RX14
RX15
RX16
RX17
RX18
RX19
RX20
RX21
RX22
RX23
RX24
RX25
RX26
RX27
RX28
RX29
RX30
RX31
Receive
Serial Data
Streams
Timing Unit
Test Port
Loopback
Data Memory
Output
MUX
Transmit
Serial Data
Streams
Internal
Registers
Connection
Memory
Microprocessor Interface
TX0
TX1
TX2
TX3
TX4
TX5
TX6
TX7
TX8
TX9
TX10
TX11
TX12
TX13
TX14
TX15
TX16
TX17
TX18
TX19
TX20
TX21
TX22
TX23
TX24
TX25
TX26
TX27
TX28
TX29
TX30
TX31
CLK F0i FE IC
DS CS R/W A0-A11 DTA D0-D15
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IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. The ST-BUS is a trademari of Mitel Corp.
1
2005 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
JANUARY 2005
DSC-5714/4
1 page  
IDT72V70210 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
COMMERCIALTEMPERATURERANGE
DESCRIPTION (CONTINUED):
The IDT72V70210 is capable of switching up to 1,024 x 1,024 channels
without blocking. Designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data, the
device maintains frame integrity in data applications and minimizes throughput
delay for voice applications on a per channel basis.
The 32 serial input streams (RX) of the IDT72V70210 can be run 2.048 Mb/s
allowing 32 channels per 125µs frame. The data rates on the output streams
(TX) are identical to those on the input stream.
With two main operating modes, Processor Mode and Connection Mode,
the IDT72V70210 can easily switch data from incoming serial streams (Data
Memory) or from the controlling microprocessor (Connection Memory). As
controlandstatusinformationiscriticalindatatransmission,theProcessorMode
is especially useful when there are multiple devices sharing the input and output
streams.
With data coming from multiple sources and through different paths, data
enteringthedeviceisoftendelayed. Tohandlethisproblem,theIDT72V70210
has a frame evaluation feature to allow individual streams to be offset from the
frame pulse in half clock-cycle intervals up to +4.5 clock cycles.
The IDT72V70210 also provides a JTAG test access port, an internal
loopback feature, memory block programming, a simple microprocessor
interface and automatic ST-BUS®/GCI sensing to shorten setup time, aid in
debugging and ease use of the device without sacrificing capabilities.
FUNCTIONAL DESCRIPTION
DATA AND CONNECTION MEMORY
All data that comes in through the RX inputs go through a serial-to-
parallelconversionbeforebeingstoredintointernalDataMemory. The8KHz
frame pulse (F0i) is used to mark the 125µs frame boundaries and to sequentially
address the input channels in Data Memory.
DataoutputontheTXstreamsmaycomefromeithertheSerialInputStreams,
RX0-31,(DataMemory)orfromthemicroprocessor(ConnectionMemory). In
the case that RX input data is to be output, the addresses in connection memory
areusedtospecifyastreamandchanneloftheinput. Theconnectionmemory
is setup in such a way that each location corresponds to an output channel for
eachparticularstream. Inthatway,morethanonechannelcanoutputthesame
data.
In Processor Mode, the microprocessor writes data to the connection
memory locations corresponding to the stream and channel that is to be
output. The lower half (8 least significant bits) of the connection memory
is output every frame until the microprocessor changes the data or mode
of the channel. By using this Processor Mode capability, the microproces-
sor can access input and output time-slots on a per channel basis.
The four most significant bits of the connection memory are used to control
per channel functions of the out put streams. Specifically, there are bits for
Processor or Connection mode, Constant or Variable delay, enables or
disables of output drivers, and controls for the Loopback function.
If the per channel OE is set to zero, only that particular channel (8-bits) will
beinthehigh-impedancestate. Ifhowever,theODEinputpinislowortheOutput
Standby Bit (OSB) in the Control Register is low, all of the outputs will be in a
high-impedance state even if a particular channel in connection memory has
enabledtheoutputforthatchannel. Inotherwords,theODEpinandOSBcontrol
bit are master output enables for the device (Table 3).
SERIAL DATA INTERFACE TIMING
The master clock frequency must always be twice the data rate. For a serial
data rates of 2.048 Mb/s, the master clock (CLK) must be at 4.096 MHz. The
input and output stream data rates will always be identical.
The IDT72V70210 provides two different interface timing modes, ST-BUS®
orGCI. TheIDT72V70210automaticallydetectsthepresenceofaninputframe
pulse and identifies it as either ST-BUS® or GCI. In ST-BUS® format, every
second falling edge of the master clock marks a bit boundary and the data is
clocked in on the rising edge of CLK, three quarters of the way into the bit cell.
In GCI format, every second rising edge of the master clock marks the bit
boundary and data is clocked in on the falling edge of CLK at three quarters of
the way into the bit cell.
INPUT FRAME OFFSET SELECTION
Input frame offset selection allows the channel alignment of individual
input streams to be offset with respect to the output stream channel
alignment (i.e. F0i). Although all input data comes in at the same speed, delays
can be caused by variable path serial backplanes and variable path lengths
which may be implemented in large centralized and distributed switching
systems. Becausedataisoftendelayedthisfeatureisusefulincompensating
for the skew between clocks.
Each input stream can have its own delay offset value by programming the
frame input offset registers (FOR, Table 8). The maximum allowable skew is +4
master clock (CLK) periods forward with a resolution of 1/2 clock period. The
output frame offset cannot be offset or adjusted.
SERIAL INPUT FRAME ALIGNMENT EVALUATION
The IDT72V70210 provides the frame evaluation (FE) input to deter-
mine different data input delays with respect to the frame pulse F0i.
A measurement cycle is started by setting the start frame evaluation (SFE)
bit low for at least one frame. When the SFE bit in the Control Register is changed
from low to high, the evaluation starts. Two frames later, the complete frame
evaluation (CFE) bit of the frame alignment register (FAR) changes from low
to high to signal that a valid offset measurement is ready to be read from bits 0
to 11 of the FAR register. The SFE bit must be set to zero before a new
measurement cycle is started.
In ST-BUS® mode, the falling edge of the frame measurement signal (FE)
is evaluated against the falling edge of the ST-BUS® frame pulse. In GCI mode,
the rising edge of FE is evaluated against the rising edge of the GCI frame pulse.
See Table 7 and Figure 1 for the description of the frame alignment register.
MEMORY BLOCK PROGRAMMING
The IDT72V70210 provides users with the capability of initializing the entire
connection memory block in two frames. To set bits 12 to 15 of every connection
memory location, first program the desired pattern in bits 5 to 8 of the Control
Register.
The block programming mode is enabled by setting the memory block
program (MBP) bit of the control register high. When the block programming
enable (BPE) bit of the Control Register is set to high, the block programming
data will be loaded into the bits 12 to 15 of every connection memory location.
The other connection memory bits (bit 0 to bit 11) are loaded with zeros. When
thememoryblockprogrammingiscomplete,thedeviceresetstheBPEbittozero.
LOOPBACK CONTROL
The loopback control (LPBK) bit of each connection memory location allows
the TX output data to be looped backed internally to the RX input for diagnostic
purposes.
If the LPBK bit is high, the associated TX output channel data is internally
looped back to the RX input channel (i.e., data from TXn channel m routes to
the RXn channel m internally); if the LPBK bit is low, the loopback feature is
5
5 Page 
IDT72V70210 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
COMMERCIALTEMPERATURERANGE
TABLE 9 — OFFSET BITS (OFn2, OFn1, OFn0, DLEn) & FRAME DELAY BITS
(FD11, FD2-0)
Input Stream
Offset
No clock period shift (Default)
+ 0.5 clock period shift
+ 1.0 clock period shift
+ 1.5 clock period shift
+ 2.0 clock period shift
+ 2.5 clock period shift
+ 3.0 clock period shift
+ 3.5 clock period shift
+ 4.0 clock period shift
+ 4.5 clock period shift
Measurement Result from
Frame Delay Bits
FD11
1
0
1
0
1
0
1
0
1
0
FD2
0
0
0
0
0
0
0
0
1
1
FD1
0
0
0
0
1
1
1
1
0
0
FD0
0
0
1
1
0
0
1
1
0
0
OFn2
0
0
0
0
0
0
0
0
1
1
Corresponding
Offset Bits
OFn1
0
0
0
0
1
1
1
1
0
0
OFn0
0
0
1
1
0
0
1
1
0
0
DLEn
0
1
0
1
0
1
0
1
0
1
ST-BUS F0i
CLK
RX Stream
RX Stream
RX Stream
RX Stream
GCI F0i
CLK
RX Stream
RX Stream
RX Stream
RX Stream
Bit 7
Bit 7
Bit 7
Bit 7
offset = 0, DLE = 0
offset = 1, DLE = 0
offset = 0, DLE = 1
offset = 1, DLE = 1
denotes the 3/4 point of the bit cell
Bit 0
Bit 0
Bit 0
Bit 0
offset = 0, DLE = 0
offset = 1, DLE = 0
offset = 0, DLE = 1
offset = 1, DLE = 1
denotes the 3/4 point of the bit cell
Figure 2. Examples for Input Offset Delay Timing
11
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11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet IDT72V70210.PDF ] | |
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