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PDF HYB39S64800 Data sheet ( Hoja de datos )
| Número de pieza | HYB39S64800 | |
| Descripción | (HYB39S64400/800/160AT) 64 MBit Synchronous DRAM | |
| Fabricantes | Siemens Semiconductor | |
| Logotipo |  |
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64 MBit Synchronous DRAM
HYB39S64400/800/160AT(L)
64MBit Synchronous DRAM
• High Performance:
-8 -8B -10 Units
fCKmax. 125 100 100 MHz
tCK3
8 10 10 ns
tAC3 6 6 7 ns
tCK2
10 12 15
ns
tAC2 6 7 8 ns
• Fully Synchronous to Positive Clock Edge
• 0 to 70 °C operating temperature
• Four Banks controlled by BA0 & BA1
• Programmable CAS Latency: 2 & 3
• Programmable Wrap Sequence: Sequential
or Interleave
• Programmable Burst Length: 1, 2, 4, 8
• full page (optional) for sequential wrap
around
• Multiple Burst Read with Single Write
Operation
• Automatic and Controlled Precharge
Command
• Data Mask for Read / Write control (x4, x8)
• Data Mask for byte control (x16)
• Auto Refresh (CBR) and Self Refresh
• Suspend Mode and Power Down Mode
• 4096 refresh cycles / 64 ms
• Random Column Address every CLK
( 1-N Rule)
• Single 3.3V +/- 0.3V Power Supply
• LVTTL Interface version
• Plastic Packages:
P-TSOPII-54 400mil width (x4, x8, x16)
• -8 version for PC100 2-2-2 applications
-8B version for PC100 3-2-3 applications
The HYB39S64400/800/160AT are four bank Synchronous DRAM’s organized as 4 banks x 4MBit
x4, 4 banks x 2MBit x8 and 4 banks x 1Mbit x16 respectively. These synchronous devices achieve
high speed data transfer rates by employing a chip architecture that prefetches multiple bits and
then synchronizes the output data to a system clock. The chip is fabricated with SIEMENS’
advanced quarter micron 64MBit DRAM process technology.
The device is designed to comply with all JEDEC standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible
depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a
single 3.3V +/- 0.3V power supply and are available in TSOPII packages.
The -8 version of this product is best suited for use on a 100 Mhz bus for both CAS latencies 2 & 3.
Semiconductor Group
1
10.98
1 page  
HYB39S64400/800/160AT(L)
64MBit Synchronous DRAM
Column address
counter
Column Addresses
A0 - A8, AP, BA0, BA1
Column address
buffer
Row Addresses
A0 - A11, BA0, BA1
Row address
buffer
Row decoder
Memory array
Bank 0
4096 x 512
x 8 bit
Row decoder
Memory array
Bank 1
4096 x 512
x 8 bit
Row decoder
Memory array
Bank 2
4096 x 512
x 8 bit
Refresh Counter
Row decoder
Memory array
Bank 3
4096 x 512
x 8 bit
Input buffer Output buffer
DQ0-DQ7
Control logic & timing generator
Block Diagram for 4 banks x 2M x 8 SDRAM
Semiconductor Group
5
5 Page 
HYB39S64400/800/160AT(L)
64MBit Synchronous DRAM
Similar to the page mode of conventional DRAM’s, burst read or write accesses on any column
address are possible once the RAS cycle latches the sense amplifiers. The maximum tRAS or the
refresh interval time limits the number of random column accesses. A new burst access can be
done even before the previous burst ends. The interrupt operation at every clock cycle is supported.
When the previous burst is interrupted, the remaining addresses are overridden by the new address
with the full burst length. An interrupt which accompanies an operation change from a read to a write
is possible by exploiting DQM to avoid bus contention.
When two or more banks are activated sequentially, interleaved bank read or write operations
are possible. With the programmed burst length, alternate access and precharge operations on two
or more banks can realize fast serial data access modes among many different pages. Once two or
more banks are activated, column to column interleave operation can be done between different
pages.
Burst Length and Sequence:
Burst Starting Address Sequential Burst Addressing
Length
(A2 A1 A0)
(decimal)
2 xx0
xx1
0, 1
1, 0
4 x00
x01
x10
x11
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
8 000
001
010
011
100
101
110
111
01234567
12345670
23456701
34567012
45670123
56701234
67012345
70123456
Full
Page
(optional)
nnn
Cn, Cn+1, Cn+2,.....
Interleave Burst Addressing
(decimal)
0, 1
1, 0
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
01234567
10325476
23016745
32107654
45670123
54761032
67452301
76543210
not supported
Refresh Mode
SDRAM has two refresh modes, Auto Refresh and Self Refresh. Auto Refresh is similar to the
CAS -before-RAS refresh of conventional DRAMs. All of banks must be precharged before applying
any refresh mode. An on-chip address counter increments the word and the bank addresses and no
bank information is required for both refresh modes.
The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE
are held high at a clock timing. The mode restores word line after the refresh and no external
precharge command is necessary. A minimum tRC time is required between two automatic
refreshes in a burst refresh mode. The same rule applies to any access command after the
automatic refresh operation.
Semiconductor Group
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HYB39S64800.PDF ] | |
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