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PDF PC7457 Data sheet ( Hoja de datos )
| Número de pieza | PC7457 | |
| Descripción | (PC7447 / PC7457) PowerPC 7457 RISC Microprocessor | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• 3000 Dhrystone 2.1 MIPS at 1.3 GHz
• Selectable Bus Clock (30 CPU Bus Dividers up to 28x)
• 13 Selectable Core-to-L3 Frequency Divisors
• Selectable MPx/60x Interface Voltage (1.8V, 2.5V)
• Selectable L3 Interface of 1.8V or 2.5V
• PD Typical 12.6W at 1 GHz at VDD = 1.3V; 8.3W at 1 GHz at VDD = 1.1V, Full Operating
Conditions
• Nap, Doze and Sleep Modes for Power Saving
• Superscalar (Four Instructions Fetched Per Clock Cycle)
• 4 GB Direct Addressing Range
• Virtual Memory: 4 Hexabytes (252)
• 64-bit Data and 32-bit Address Bus Interface
• Integrated L1: 32 KB Instruction and 32 KB Data Cache
• Integrated L2: 512 KB
• 11 Independent Execution Units and Three Register Files
• Write-back and Write-through Operations
• fINT Max = 1 GHz (1.2 GHz to be Confirmed)
• fBUS Max = 133 MHz/166 MHz
Description
This document is primarily concerned with the PowerPC™ PC7457; however, unless
otherwise noted, all information here also applies to the PC7447. The PC7457 and
PC7447 are implementations of the PowerPC microprocessor family of reduced
instruction set computer (RISC) microprocessors. This document describes pertinent
electrical and physical characteristics of the PC7457.
The PC7457 is the fourth implementation of the fourth generation (G4) microproces-
sors from Motorola. The PC7457 implements the full PowerPC 32-bit architecture and
is targeted at networking and computing systems applications. The PC7457 consists
of a processor core, a 512 Kbyte L2, and an internal L3 tag and controller which sup-
port a glueless backside L3 cache through a dedicated high-bandwidth interface. The
PC7447 is identical to the PC7457 except it does not support the L3 cache interface.
The core is a high-performance superscalar design supporting a double-precision
floating-point unit and a SIMD multimedia unit. The memory storage subsystem sup-
ports the MPX bus interface to main memory and other system resources. The L3
interface supports 1, 2, or 4M bytes of external SRAM for L3 cache and/or private
memory data. For systems implementing 4M bytes of SRAM, a maximum of 2M bytes
may be used as cache; the remaining 2M bytes must be private memory.
Note that the PC7457 is a footprint-compatible, drop-in replacement in a PC7455
application if the core power supply is 1.3V.
PowerPC 7457
RISC
Microprocessor
PC7457/47
Preliminary
Specification
α-site
Rev. 5345B–HIREL–02/04
1 page  
5345B–HIREL–02/04
PC7457/47 [Preliminary]
– Four integer units (IUs) that share 32 GPRs for integer operands
Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer
instructions except multiply, divide, and move to/from special-purpose
register instructions
IU2 executes miscellaneous instructions including the CR logical operations,
integer multiplication and division instructions, and move to/from special-
purpose register instructions
– Five-stage FPU and a 32-entry FPR file
Fully IEEE 754-1985-compliant FPU for both single- and double-precision
operations
Supports non-IEEE mode for time-critical operations
Hardware support for denormalized numbers
Thirty-two 64-bit FPRs for single- or double-precision operands
– Four vector units and 32-entry vector register file (VRs)
Vector permute unit (VPU)
Vector integer unit 1 (VIU1) handles short-latency AltiVec™ integer
instructions, such as vector add instructions (vaddsbs, vaddshs, and
vaddsws, for example)
Vector integer unit 2 (VIU2) handles longer-latency AltiVec integer
instructions, such as vector multiply add instructions (vmhaddshs,
vmhraddshs, and vmladduhm, for example)
Vector floating-point unit (VFPU)
– Three-stage load/store unit (LSU)
Supports integer, floating-point, and vector instruction load/store traffic
Four-entry vector touch queue (VTQ) supports all four architected AltiVec
data stream operations
Three-cycle GPR and AltiVec load latency (byte, half-word, word, vector)
with one-cycle throughput
Four-cycle FPR load latency (single, double) with one-cycle throughput
No additional delay for misaligned access within double-word boundary
Dedicated adder calculates effective addresses (EAs)
Supports store gathering
5
5 Page 
PC7457/47 [Preliminary]
Detailed
Specification
Scope
Applicable
Documents
This specification describes the specific requirements for the microprocessor PC7457 in
compliance with Atmel standard screening.
1. MIL-STD-883: Test methods and procedures for electronics
2. MIL-PRF-38535: Appendix A: General specifications for microcircuits
Requirements
General
The microcircuits are in accordance with the applicable documents and as specified
herein.
Design and Construction
Terminal Connections
Depending on the package, the terminal connections are as shown in Table 16, Table 3
and Figure 2.
Absolute Maximum
Ratings
Table 2. Absolute Maximum Ratings(1)
Symbol
Characteristic
Maximum Value
Unit
VDD(2)
AVDD(2)
OVDD(3)(4)
OVDD(3)(5)
GVDD(3)(6)
GVDD(3)(7)
GVDD(3)(8)
VIN(9)(10)
VIN(9)(10)
Core supply voltage
PLL supply voltage
Processor bus supply voltage
L3 bus supply voltage
Input voltage
BVSEL = 0
BVSEL = HRESET or OVDD
L3VSEL = ¬HRESET
L3VSEL = 0
L3VSEL = HRESET or GVDD
Processor bus
L3 bus
-0.3 to 1.60
-0.3 to 1.60
-0.3 to 1.95
-0.3 to 2.7
-0.3 to 1.65
-0.3 to 1.95
-0.3 to 2.7
-0.3 to OVDD + 0.3
-0.3 to GVDD + 0.3
V
V
V
V
V
V
V
V
V
VIN
JTAG signals
-0.3 to OVDD + 0.3
V
TSTG
Notes:
Storage temperature range
-55 to 150
°C
1. Functional and tested operating conditions are given in Table 3 on page 12. Absolute maximum ratings are stress ratings
only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability
or cause permanent damage to the device.
2. Caution: VDD/AVDD must not exceed OVDD/GVDD by more than 1V during normal operation; this limit may be exceeded for a
maximum of 20 ms during power-on reset and power-down sequences.
3. Caution: OVDD/GVDD must not exceed VDD/AVDD by more than 2V during normal operation; this limit may be exceeded for a
maximum of 20 ms during power-on reset and power-down sequences.
4. BVSEL must be set to 0, such that the bus is in 1.8V mode.
5. BVSEL must be set to HRESET or 1, such that the bus is in 2.5V mode.
6. L3VSEL must be set to ¬HRESET (inverse of HRESET), such that the bus is in 1.5V mode.
5345B–HIREL–02/04
11
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| PDF Descargar | [ Datasheet PC7457.PDF ] | |
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