PDF ICS307 Data sheet ( Hoja de datos )

Número de pieza	ICS307
Descripción	Serially Programmable Clock Source
Fabricantes	Integrated Circuit Systems
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No Preview Available ! ICS307 Serially Programmable Clock Source Description The ICS307-01 and ICS307-02 are versatile serially programmable clock sources which take up very little board space. They can generate any frequency from 6 to 200 MHz, and have a second configurable output. The outputs can be reprogrammed on the fly, and will lock to a new frequency in 10 ms or less. Smooth transitions (in which the clock duty cycle remains roughly 50%) are guaranteed if the output divider is not changed. The devices include a PDTS pin which tri-states the output clocks and powers down the entire chip. The ICS307-02 features a default clock output at start-up and is recommended for all new designs. Features • Packaged as 16 pin narrow SOIC • Highly accurate frequency generation • Serially programmable: user determines the output frequency via a 3 wire interface. • Eliminates need for custom quartz • Input crystal frequency of 5 - 27 MHz • Output clock frequencies up to 200 MHz • Power Down Tri-State mode • Very low jitter • Operating voltages of 3.0 to 5.5 V • 25 mA drive capability at TTL levels • Industrial temperature available Block Diagram VDD GND SCLK DATA STROBE Crystal or clock input X1/ICLK X2 Shift Register R6:R0 TTL 2 C1:C0 3 S2:S0 2 F1:F0 7 9 V8:V0 VCO Divider Reference Divider Phase Comparator, Charge Pump, and Loop Filter VCO Output Buffer S2:S0 3 Output Divider Crystal Oscillator C1:C0 Function Select Output Buffer 2 F1:F0 TTL CLK1 PDTS CLK2 MDS 307 D 1 Revision 042501 Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel •www.icst.com 1 page ICS307 Serially Programmable Clock Source Configuring the ICS307 The ICS307 can be programmed to set the output functions and frequencies. The three data bytes are written to the DATA pin, in this order: C1 C0 TTL F1 F0 S2 S1 S0 V8 V7 V6 V5 V4 V3 V2 V1 MSB LSB MSB LSB C1 is loaded into the port first and R0 last. V0 R6 R5 R4 R3 R2 R1 R0 MSB LSB R6:R0 V8:V0 S2:S0 F1:F0 TTL C1:C0 Reference Divider Word (RDW) VCO Divider Word (VDW) Output Divider Select (OD) Function of CLK2 Output Duty Cycle Setting Internal Load Capacitance for Crystal Power up default values for ICS 307-02 00 100011 00 000100 The input frequency will come from both outputs. 00 000110 Programming Example To generate 66.66 MHz from a 14.31818 MHz input, the RDW should be 59, the VDW should be 276, and the Output Divide is 2. Selecting the minimum internal load capacitance, CMOS duty cycle, and CLK2 to be OFF means that the following three bytes are sent to the ICS307: 00110001 Byte 1 10001010 Byte 2 00111011 Byte 3 As shown in Figure 2, after these 24 bits are clocked into the ICS307, taking STROBE high will send this data to the internal latch, and the CLK output will lock within 10 ms. NOTE: If STROBE is in the high state and SCLK is pulsed, DATA is clocked directly to the internal latch and the output conditions will change accordingly. Although this will not damage the ICS307, it is recommended that STROBE be kept low while DATA is being clocked into the ICS307 in order to avoid unintended changes on the output clocks. MDS 307 D 5 Revision 042501 Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel •www.icst.com 5 Page

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