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PDF K4S1G0732B-TC75 Data sheet ( Hoja de datos )
| Número de pieza | K4S1G0732B-TC75 | |
| Descripción | SDRAM stacked 1Gb B-die | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de K4S1G0732B-TC75 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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SDRAM stacked 1Gb B-die (x8)
CMOS SDRAM
stacked 1Gb B-die SDRAM Specification
Revision 1.1
February 2004
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.1 February 2004
1 page  
SDRAM stacked 1Gb B-die (x8)
PIN CONFIGURATION (Top view)
CMOS SDRAM
VDD
DQ0
VDDQ
N.C
DQ1
VSSQ
N.C
DQ2
VDDQ
N.C
DQ3
VSSQ
N.C
VDD
CS1
WE
CAS
RAS
CS0
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 VSS
53 DQ7
52 VSSQ
51 N.C
50 DQ6
49 VDDQ
48 N.C
47 DQ5
46 VSSQ
45 N.C
44 DQ4
43 VDDQ
42 N.C
41 VSS
40 CKE1
39 DQM
38 CLK
37 CKE0
36 A12
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 VSS
54Pin TSOP
(400mil x 875mil)
(0.8 mm Pin pitch)
PIN FUNCTION DESCRIPTION
Pin
CLK
Name
System clock
CS0~1
Chip select
CKE0~1
Clock enable
A0 ~ A12
Address
BA0 ~ BA1 Bank select address
RAS
Row address strobe
CAS
Column address strobe
WE Write enable
DQM
Data input/output mask
DQ0 ~7
VDD/VSS
VDDQ/VSSQ
Data input/output
Power supply/ground
Data output power/ground
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9, CA11
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
Rev. 1.1 February 2004
5 Page 
SDRAM stacked 1Gb B-die (x8)
VDD Clamp @ CLK, CKE, CS, DQM & DQ
VDD (V)
I (mA)
0.0 0.0
0.2 0.0
0.4 0.0
0.6 0.0
0.7 0.0
0.8 0.0
0.9 0.0
1.0 0.23
1.2 1.34
1.4 3.02
1.6 5.06
1.8 7.35
2.0 9.83
2.2 12.48
2.4 15.30
2.6 18.31
CMOS SDRAM
Minimum VDD clamp current
(Referenced to VDD)
20
15
10
5
0
0123
Voltage
I (mA)
VSS Clamp @ CLK, CKE, CS, DQM & DQ
VSS (V)
I (mA)
-2.6 -57.23
-2.4 -45.77
-2.2 -38.26
-2.0 -31.22
-1.8 -24.58
-1.6 -18.37
-1.4 -12.56
-1.2 -7.57
-1.0 -3.37
-0.9 -1.75
-0.8 -0.58
-0.7 -0.05
-0.6 0.0
-0.4 0.0
-0.2 0.0
0.0 0.0
-3
0
-10
-20
-30
-40
-50
-60
Minimum VSS clamp current
-2 -1
Voltage
I (mA)
0
Rev. 1.1 February 2004
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet K4S1G0732B-TC75.PDF ] | |
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