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PDF DS1318 Data sheet ( Hoja de datos )
| Número de pieza | DS1318 | |
| Descripción | Parallel-Interface Elapsed Time Counter | |
| Fabricantes | Dallas Semiconducotr | |
| Logotipo |  |
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Rev 0; 2/04
Parallel-Interface Elapsed Time Counter
General Description
The DS1318 parallel-interface elapsed time counter
(ETC) is a 44-bit counter that maintains the amount of
time that the device operates from main and/or backup
power or during an external event. The internal
frequency of the counter clock is 4.096kHz, which pro-
vides a 244µs resolution and a maximum count of over
136 years. A built-in power-sense circuit detects power
failures, automatically switches to the backup supply,
and controls the timer. If an external event timer is
desired, the control input EXT can control the counter
operation. An open-drain output provides an interrupt,
and a square-wave output provides a programmable
square wave. The DS1318 is accessed through a byte-
wide parallel interface, and operates over the industrial
temperature range.
Power Meters
Industrial Controls
Servers
Applications
Typical Operating Circuit
Features
♦ Byte-Wide Parallel Interface
♦ 44-Bit Binary Counter Provides Timer with 244µs
Resolution
♦ Automatic Power-Fail Detect and Switch Circuitry
Selects Power Source from the Primary Power
and the Battery, and Write Protects the Internal
Registers
♦ Internal Power-Fail Circuit Allows Timer to
Provide Primary or Battery Operation Times
♦ Timer can Alternately Provide an Event Timer of
Either an Active-High or Active-Low Pulse
♦ Interrupt Output Generated Periodically or When
the Upper 32 Bits of the Counter Match an Alarm
Register
♦ Square-Wave Output with 16 Selectable
Frequencies from 32.768kHz to 0.5Hz
♦ +3.3V Operation
♦ Industrial Temperature Range: -40°C to +85°C
PART
DS1318
Ordering Information
TEMP RANGE
PIN-
PACKAGE
-40°C to +85°C
24 TSSOP,
4.4mm
TOP MARK
DS1318
Pin Configuration
VCC
RPU
VCC
SQW
IRQ
WE EXT
OE
CPU
CE
DS1318
VBAT
A3–A0
X1
DQ–DQ7
GND X2
0.1µF
EXTERNAL
COUNTER
ENABLE
(EVENT TIMER)
TOP VIEW
X1
X2
GND
EXT
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
DS1318
TSSOP
24 VCC
23 VBAT
22 IRQ
21 SQW
20 WE
19 OE
18 CE
17 DQ7
16 DQ6
15 DQ5
14 DQ4
13 DQ3
______________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
Parallel-Interface Elapsed Time Counter
Power-Up/Power-Down Timing
VCC
VPF(MAX)
VPF(MIN)
tVCCF
tVCCR
tREC
INPUTS
RECOGNIZED
OUTPUTS
VALID
DON'T CARE
HIGH-Z
RECOGNIZED
VALID
POWER-UP/POWER-DOWN CHARACTERISTICS
(TA = -40°C to +85°C) (Note 1)
PARAMETER
Recovery at Power-Up
SYMBOL
tREC (Note 9)
CONDITIONS
VCC Fall Time; VPF(MAX) to
VPF(MIN)
tVCCF
VCC Rise Time; VPF(MIN) to
VPF(MAX)
tVCCR
CAPACITANCE
(TA = +25°C)
PARAMETER
Capacitance on All Input Pins
Capacitance on IRQ, SQW, and
DQ Pins
SYMBOL
CIN
CIO
CONDITIONS
MIN TYP MAX UNITS
150 ms
300 µs
0 µs
MIN TYP MAX UNITS
10 pF
10 pF
_____________________________________________________________________ 5
5 Page 
Parallel-Interface Elapsed Time Counter
BIT 7
TE
BIT 6
ENOSC
BIT 5
CCFG1
BIT 4
CCFG0
Special-Purpose Registers
The DS1318 has three additional registers (control A,
control B, and status) that control the clock, alarms,
square wave, and interrupt output. The subseconds0
register has a square-wave synchronization (SQWS) bit
in the bit 0 location. Writing the SQWS bit to 1 clears
the square-wave prescaler and holds it in reset. Only
the frequencies below 4096Hz are reset. Writing the bit
back to 0 takes the prescaler out of reset and starts the
square wave running.
Bit 7: Transfer Enable (TE). When TE is set to logic 1,
the DS1318 continues to update the user copy of the
time value as it receives 4,096Hz clock pulses from the
oscillator. To ensure reading valid time data from the
part, the user should set TE to logic 0 before reading
registers 00–05h. TE must be enabled (logic 1) for at
least 244µs to ensure that a transfer occurs. Note that
because of the 244µs restriction, sequential values of
the subseconds0 register cannot be read when TE
is used.
It is possible that TE could be set to logic 0 while a
transfer is taking place. In that case, the buffered data
could be invalid. To prevent this, the UIP bit, described
later, should be used. To write data to the clock regis-
ters, the user should set TE to logic 0, write the regis-
ters, and set TE to logic 1.
Bit 6: Enable Oscillator (ENOSC). When ENOSC is set
to logic 1, the DS1318 crystal oscillator becomes
enabled. Actual startup time for the oscillator depends on
many external variables and is not a specified parameter.
Bits 5, 4: Clock Configuration 1, 0 (CCFG1, CCFG0).
These bits determine which of the four possible modes
the DS1318 uses to clock its timekeeping registers:
Control Register A (0Ah)
BIT 3
EPOL
BIT 2
SQWE
BIT 1
PIE
BIT 0
AIE
Bit 3: External Polarity (EPOL). This bit controls the
polarity on the EXT pin input when the CCFG1 and
CCFG0 bits are equal to 0 and 1, respectively. When
EPOL is set to logic 1, the registers count when the EXT
pin is 1. When EPOL is set to logic 0, the registers
count when the EXT pin is logic 0.
Bit 2: Square-Wave Enable (SQWE). When SQWE is
set to logic 1, a frequency determined by the SRSx bits
in control register B (0Bh) is output on the SQW pin.
When SQWE is logic 0, the SQW pin is always 0. When
the part is in power-fail, the SQW pin is always high-
impedance. The square-wave output uses a separate
prescaler from the one used by PF, IRQ, UIP, and the
up counter. The SQWS bit in control register A can be
used to synchronize the square-wave output to within
244µs of the other events.
Bit 1: Periodic Interrupt Enable (PIE). When PIE is set
to logic 1, the DS1318 sets the IRQ pin low whenever
the PF flag is set to 1. When PIE is 0, the PF flag does
not affect the IRQ pin.
Bit 0: Alarm Interrupt Enable (AIE). When AIE is set to
logic 1, the DS1318 sets the IRQ pin low whenever the
ALMF flag is set to 1. When AIE is 0, the ALMF flag
does not affect the IRQ pin.
CCFG1 CCFG0
MODE
0 0 Always clocks the registers (normal mode)
Clocks when the EXT pin is “active” and
0 1 VCC is greater than VPF (event-timer mode,
depends on EPOL bit)
1
0
Clocks registers when part is running on
VCC
1 1 Clocks registers when part is running on
VBAT
____________________________________________________________________ 11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet DS1318.PDF ] | |
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