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PDF TH58100FTI Data sheet ( Hoja de datos )
| Número de pieza | TH58100FTI | |
| Descripción | TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS | |
| Fabricantes | Toshiba Semiconductor | |
| Logotipo |  |
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TH58100FTI
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
1-GBIT (128M × 8 BITS) CMOS NAND E2PROM
DESCRIPTION
The TH58100 is a single 3.3 V 1-Gbit (1,107,296,256) bit NAND Electrically Erasable and Programmable
Read-Only Memory (NAND E2PROM) organized as 528 bytes × 32 pages × 8192 blocks. The device has a 528-byte
static register which allows program and read data to be transferred between the register and the memory cell array
in 528-byte increments. The Erase operation is implemented in a single block unit (16 Kbytes + 512 bytes: 528 bytes
× 32 pages).
The TH58100 is a serial-type memory device which utilizes the I/O pins for both address and data input/output as
well as for command inputs. The Erase and Program operations are automatically executed making the device most
suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and
other systems which require high-density non-volatile memory data storage.
FEATURES
• Organization
Memory cell allay 528 × 128K × 8 × 2
Register
528 × 8
Page size
528 bytes
Block size
(16K + 512) bytes
• Modes
Read, Reset, Auto Page Program
Auto Block Erase, Status Read
Multi Block Program, Multi Block Erase
• Mode control
Serial input/output
Command control
PIN ASSIGNMENT (TOP VIEW)
• Power supply
VCC = 2.7 V to 3.6 V
• Program/Erase Cycles 1E5 cycle (with ECC)
• Access time
Cell array to register 25 µs max
Serial Read Cycle 50 ns min
• Operating current
Read (50 ns cycle) 10 mA typ.
Program (avg.)
10 mA typ.
Erase (avg.)
10 mA typ.
Standby
100 µA
• Package
TSOPI48-P-1220-0.50 (Weight: 0.53 g typ.)
PIN NAMES
NC
NC
NC
NC
NC
GND
RY / BY
RE
CE
NC
NC
VVNCSCCS
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
1
48 NC
I/O1 to I/O8 I/O port
2 47 NC
3
www.DataSheet4U.com4
46 NC
45 NC
CE Chip enable
5
6
44 I/O8
43 I/O7
WE Write enable
7
8
42 I/O6
41 I/O5
RE Read enable
9
10
40 NC
39 NC
CLE Command latch enable
11
12
13
14
38 NC
37
36
35
NVVCSCSC
ALE Address latch enable
WP Write protect
15 34 NC
16
33 NC
RY/BY
Ready/Busy
17 32 I/O4
18
31 I/O3
GND
Ground input
19 30 I/O2
20
21
29 I/O1
28 NC
VCC
Power supply
22
23
27 NC
26 NC
VSS Ground
24 25 NC
000707EBA1
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid
situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide
for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document
shall be made at the customer’s own risk.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its
use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or
others.
• The information contained herein is subject to change without notice.
2001-03-05 1/43
1 page  
TH58100FTI
Note: (1) CE High to Ready time depends on the pull-up resistor tied to the RY/BY pin.
(Refer to Application Note (9) toward the end of this document.)
(2) Sequential Read is terminated when tCEH is greater than or equal to 100 ns. If the RE to CE delay
is less than 30 ns, RY/BY signal stays Ready.
tCEH ≥ 100 ns
* *: VIH or VIL
CE
RE
525 526 527 A
A : 0 to 30 ns → Busy signal is not output.
RY/BY
Busy
tCRY
PROGRAMMING AND ERASING CHARACTERISTICS (Ta = - 40° to 85°C, VCC = 2.7 V to 3.6 V)
SYMBOL
PARAMETER
MIN
tPROG
tDBSY
Programming Time
Dummy Busy Time for Multi Block
Programming
tMBPBSY
N
Multi Block Program Busy Time
Number of Programming Cycles on Same
Page
tBERASE
Block Erasing Time
(1): Refer to Application Note (12) toward the end of this document.
TYP.
200
2
200
2
MAX
1000
10
1000
3
10
UNIT
µs
µs
µs
ms
NOTES
(1)
2001-03-05 5/43
5 Page 
Sequential Read (1) Timing Diagram
CLE
TH58100FTI
CE
WE
ALE
RE
I/O1
to I/O8
00H
RY/BY
At0o At9o A1to7 At2o5
A7 A16 A24 A26
Column
Page
address address
NM
tR
N N+1 N+2
527
tR
012
Page M
access
Page M + 1
access
: VIH or VIL
Sequential Read (2) Timing Diagram
CLE
527
CE
WE
ALE
RE
I/O1
to I/O8
01H
RY/BY
A0 A9 A17 A25
to to to to
A7 A16 A24 A26
Column
Page
address address
NM
tR
256 + 256 + 256 +
N N+1 N+2
527
tR
012
527
Page M
access
Page M + 1
access
: VIH or VIL
2001-03-05
11/43
11 Page | ||
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| PDF Descargar | [ Datasheet TH58100FTI.PDF ] | |
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