PDF AD6650 Data sheet ( Hoja de datos )

Número de pieza	AD6650
Descripción	Diversity IF to Baseband GSM/EDGE Narrowband Receiver
Fabricantes	Analog Devices
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No Preview Available ! AD6650 Diversity IF-to-Baseband GSM/EDGE Narrow-Band Receiver AD6650 FEATURES 116 dB dynamic range Digital VGA I/Q demodulators Active low-pass filters Dual wideband ADC Programmable decimation and channel filters VCO and phase-locked loop circuitry Serial data output ports Intermediate frequencies of 70 MHz to 260 MHz 10 dB noise figure +43 dBm input IP2 at 70 MHz IF −9.5 dBm input IP3 at 70 MHz IF 3.3 V I/O and CMOS core Microprocessor interface JTAG boundary scan APPLICATIONS PHS or GSM/EDGE single carrier, diversity receivers Microcell and picocell systems Wireless local loop Smart antenna systems Software radios In-building wireless telephony PRODUCT DESCRIPTION The AD6650 is a diversity intermediate frequency-to-baseband (IF-to-baseband) receiver for GSM/EDGE. This narrow-band receiver consists of an integrated DVGA, IF-to-baseband I/Q demodulators, low-pass filtering, and a dual wideband ADC. The chip can accommodate IF input from 70 MHz to 260 MHz. The receiver architecture is designed such that only one external surface acoustic wave (SAW) filter for main and one for diversity are required in the entire receive signal path to meet GSM/EDGE blocking requirements. Digital decimation and filtering circuitry provided on-chip remove unwanted signals and noise outside the channel of interest. Programmable RAM coefficient filters allow antialiasing, matched filtering, and static equalization functions to be combined in a single cost-effective filter. The output of the channel filters is provided to the user via serial output I/Q data streams. AIN VGA AIN CPOUT LF VLDO PLL/ VCO BIN VGA BIN 0 /4 90 FUNCTIONAL BLOCK DIAGRAM TWEAK GAIN DAC I LPF MUX LPF Q AGC RELIN CTRL 12-BIT ADC COARSE DCC LP FILTER 4TH ORDER CIC 7TH ORDER IIR REF LPF LPF JTAG Q MUX 12-BIT ADC COARSE DCC I DAC TWEAK GAIN CLK DIVIDER AGC RELIN CTRL 4TH ORDER CIC 7TH ORDER IIR LP FILTER AD6650 GSM/ EDGE IF RECEIVER PROG. FIR (RCF) FINE DCC BIST SERIAL PORT SCLK SDFS SDO0 SDO1 DR PROG. FIR (RCF) FINE DCC BIST MICRO Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006–2007 Analog Devices, Inc. All rights reserved. 1 page AD6650 Parameter f = 150 MHz Coarse DC Correction Noise Figure2 Input IP22 Input IP32 Image Rejection Full-Scale Input Power Input Impedance f = 200 MHz Coarse DC Correction Noise Figure2 Input IP22 Input IP32 Image Rejection Full-Scale Input Power Input Impedance f = 250 MHz Coarse DC Correction Noise Figure2 Input IP22 Input IP32 Image Rejection Full-Scale Input Power Input Impedance Temp Full Full Full Full Full Full Full Full Full 1 See Figure 40 and Figure 41 for additional PSRR specifications. 2 This measurement applies for maximum gain (36 dB). Test Level V V IV IV IV V V V V IV IV IV V V V V VII VII VII V V Min Typ −70 10 24 37 −15 −11.5 −46.5 4 169.3 − j59.2 −70 10 24 35 −16 −12 −46.5 4 159.3 − j66.9 −70 10 24 33 −16 −13 −45 4 137.1 − j72.7 Max Unit dB dB dBm dBm −33 dBc dBm Ω dB dB dBm dBm −33 dBc dBm Ω dB dB dBm dBm −33 dBc dBm Ω DIGITAL SPECIFICATIONS AVDD and DVDD = 3.3 V, CLK = 52 MSPS, unless otherwise noted. Table 2. Parameter DVDD AVDD TAMBIENT1 Temp Full Full Test Level IV IV IV Min Typ Max Unit 3.0 3.3 3.45 V 3.0 3.3 3.45 V −25 +25 +85 °C 1 The AD6650 is guaranteed fully functional from −40°C to +85°C. All ac minimum specifications are guaranteed from −25°C to +85°C, but degrade slightly from −25°C to −40°C. Rev. A \| Page 4 of 44 5 Page AD6650 ABSOLUTE MAXIMUM RATINGS Table 7. Parameter Supply Voltage Input Voltage Output Voltage Swing Load Capacitance Junction Temperature Under Bias Storage Temperature Range Lead Temperature (5 sec) Rating −0.3 V to +3.6 V −0.3 V to +3.6 V −0.3 V to VDDIO + 0.3 V 200 pF 125°C −65°C to +150°C 280°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL CHARACTERISTICS 121-lead chip scale package ball grid array: θJA = 22.8°C/W, no airflow, measurements made in the horizontal position on a 4-layer board. θJA = 20.2°C/W, 200 LFPM airflow, measurements made in the horizontal position on a 4-layer board. θJA = 20.7°C/W, no airflow, soldered on an 8-layer board with two layers dedicated as ground planes. ESD CAUTION Rev. A \| Page 10 of 44 11 Page

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