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PDF IDT79RC32334 Data sheet ( Hoja de datos )
| Número de pieza | IDT79RC32334 | |
| Descripción | (IDT79RC32332 / IDT79RC32334) Integrated Communications Processors | |
| Fabricantes | Integrated Device Technology | |
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IDT79RC32334 and IDT79RC32332
Integrated Communications
Processors
(Y Revision)
RISCore™ 32300 Family
www. User Reference ManualJune2002
DataS 2975 Stender Way, Santa Clara, California 95054
Telephone: (800) 345-7015 • TWX: 910-338-2070 • FAX: (408) 330-1748
h Printed in U.S.A.
eet4U.com©2001 Integrated Device Technology, Inc.
1 page  
About This Manual
Notes
Revision History
Revision History
November 15, 2000: Initial publication.
February 5, 2001: In Chapter 12, separated PCI CPU Memory and I/O Space 1 Base Register section
into two sections, one dealing with CPU Memory and the other with CPU I/O, and changed bit description to
reflect CPU I/O Base uses [23:20] instead of [31:28].
February 26, 2001: Changed alternate function for uart_tx[0] from PIO[3] to PIO[1] in Table 1.2 and G.4.
In Chapter 15, clarified that timer_tc_n[0] is not present in the RC32332 and added a reference in the Signal
Definitions section to Tables G.2 and G.3. In Appendix G, added two tables (G.2 and G.3) to highlight the
differences in PIO pin name assignments between the RC32334 and RC32332.
April 2, 2001: Made the following changes in Chapter 18: added system clock formula under Serial
Peripheral Clock Register section; removed “active” from description for bit 2 in table 18.4; changed SPSE
register to SPSR register in Table 18.6; in Master Programming Example, item 1, changed formula in paren-
theses to 3.7 MHz (67/ [(8+1) * 2]); in Master Programming Example, item 2, changed formula in paren-
theses to 3.7 / 2 = 1.85 MHz.
May 17, 2001: Table 17.6, “Interrupt Identity Register Fields and Descriptions,” has been revised to
show that for bits 3:1 (Current Interrupt field) the value 111 has the same status and priority level as the
value 011. Also, in Table 11.2, under SDRAM Organization column, 2nd category from the bottom, the data
now reads “2 Mb x 16 x 4 banks” instead of “4 Mb x 16 x 4 banks.” Finally, in Table 11.6, for bit 28 (SDRAM
Bank Size field), the value descriptions now omit any reference to 16M-bit and 64M-bit. These references
were confusing because the RC32334 and RC32332 devices also support 128M-bit SDRAMs.
July 26, 2001: In Chapter 10, the bit address for mem_addr[25:2] was changed from 40000 to 3C00000
in Figures 10.6 through 10.30.
June 4, 2002: Made the following changes based on the introduction of Y silicon: Chapter 8, Internal
Bus—changes in bit 7 description in Table 8.12, changes in Table 8.13. Chapter 11, SDRAM Controller—
added more SDRAM address multiplexing and control registers (SDRAM Secondary Control), changes to
Tables 11.1 and 11.2, changes in SDRAM Initialization section. Chapter 12, PCI Interface—added CPU to
PCI and PCI to CPU mapping diagrams, new Memory/IO Space Base register and PCI Memory/IO Base
Address registers, Target FIFOs are 16 words deep, added PCI Target Control Register and New Feature
sections, added additional fields in PCI Arbitration Register (Table 12.15), added 2 new base address regis-
ters, revised Tables 12.1, 12.7, and 12.12, changed Reset for System Identification Number from 00h to
01h (Table 12.24). Chapter 13, DMA Controllers—added New Feature Configuration register, added
SDRAM to PCI Arbitration Algorithm field, and revised function description for interrupt_n[3] and n[4] pins in
Table 13.3. PIO chapter—added New Feature Register. Clocking, Reset and Initialization chapter—revised
description in first row of Table 19.1.
79RC32334/332 User Reference Manual
iii
June 4, 2002
5 Page 
Table of Contents
Notes
Bus Time-Out Counters ...............................................................................................................8-5
Bus Error Timers..........................................................................................................................8-5
Register Descriptions...................................................................................................................8-5
Interface Control Registers ..........................................................................................................8-6
CPU Port-Width Control Register: Virtual Address 0xFFFF_E200 ....................................8-6
CPU Bus Turnaround (BTA) Control Register: Virtual Address 0xFFFF_E204..................8-8
CPU Bus Error Address Register (Read Only): Virtual Address 0xFFFF_E208 ................8-9
BTA Control Register..........................................................................................................8-9
Address Latch Timing Register.................................................................................................. 8-11
Arbitration Register ..........................................................................................................8-12
BusError Control Register ................................................................................................8-12
BusError Address Register ..............................................................................................8-12
SysID Register .................................................................................................................8-14
9 External Local Bus Interface
Introduction ..................................................................................................................................9-1
Operation .....................................................................................................................................9-1
Variable Port-Width Interface.......................................................................................................9-2
Debug Signals ............................................................................................................................9-4
10 Memory Controller
Introduction ................................................................................................................................10-1
List of Features ..........................................................................................................................10-1
Block Diagram ...........................................................................................................................10-1
Functional Overview ..................................................................................................................10-2
Memory Controller Operation ....................................................................................................10-2
Integrated Processor Generated Transactions ................................................................10-2
DMA Controller or PCI Bridge Generated Transactions...................................................10-2
Chip Selects .....................................................................................................................10-3
Transceiver Control Interface ...........................................................................................10-3
Using 8- or 16-bit Boot PROMs .................................................................................................10-3
Wait-State Generator (WSG).....................................................................................................10-4
Address Decoding .....................................................................................................................10-4
Memory Type and Port-Width Size Support ..............................................................................10-5
Port-Width Size..........................................................................................................................10-6
I/O Width Support.............................................................................................................10-7
Programmable Wait-State Generator ........................................................................................10-7
External Wait-State Behavior ...........................................................................................10-7
Bus Error Recovery ...................................................................................................................10-8
Signal Descriptions ....................................................................................................................10-8
Register Definitions...................................................................................................................10-9
Memory MSB Base Address Register for Banks 1:0......................................................10-10
Memory MSB Bank Mask Registers for Banks 1:0 ........................................................10-10
Memory Control Register for Banks 5:0 ......................................................................... 10-11
Timing Diagrams......................................................................................................................10-12
79RC32334/332 User Reference Manual
ix
June 4, 2002
11 Page | ||
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| PDF Descargar | [ Datasheet IDT79RC32334.PDF ] | |
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