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PDF HI-8583 Data sheet ( Hoja de datos )
| Número de pieza | HI-8583 | |
| Descripción | (HI-8582 / HI-8583) ARINC 429 SYSTEM ON A CHIP | |
| Fabricantes | Holt Integrated Circuits | |
| Logotipo |  |
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HI-8582, HI-8583
June 2001
ARINC 429 System on a Chip
GENERAL DESCRIPTION
The HI-8582 from Holt Integrated Circuits is a silicon gate
CMOS device for interfacing a 16-bit parallel data bus
directly to the ARINC 429 serial bus. The HI-8582 design
offers many enhancements to the industry standard HI-
8282 architecture. The device provides two receivers each
with label recognition, 32 by 32 FIFO, and analog line
receiver. Up to 16 labels may be programmed for each
receiver. The independent transmitter has a 32 by 32 FIFO
and a built-in line driver. The status of all three FIFOs can
be monitored using the external status pins, or by polling
the HI-8582’s status register. Other new features include a
programmable option of data or parity in the 32nd bit, and
the ability to unscramble the 32 bit word. Also, versions
are available with different values of input resistance and
output resistance to allow users to more easily add external
lightning protection circuitry. The device can be used at
nonstandard data rates when an option pin, NFD, is
invoked.
The 16-bit parallel data bus exchanges the 32-bit ARINC
data word in two steps when either loading the transmitter
or interrogating the receivers. The databus, and all control
signals are CMOS and TTL compatible.
The HI-8582 applies the ARINC protocol to the receivers
and transmitter. Timing is based on a 1 Megahertz clock.
Although the line driver shares a common substrate with
the receivers, the design of the physical isolation does not
allow parasitic crosstalk, and thereby achieves the same
isolation as common hybrid layouts.
APPLICATIONS
! Avionics data communication
! Serial to parallel conversion
! Parallel to serial conversion
FEATURES
! ARINC specification 429 compatible
! Dual receiver and transmitter interface
! Analog line driver and receivers connect
directly to ARINC bus
! Programmable label recognition
! On-chip 16 label memory for each receiver
! 32 x 32 FIFOs each receiver and transmitter
! Independent data rate selection for
transmitter and each receiver
! Status register
! Data scramble control
! 32nd transmit bit can be data or parity
! Self test mode
! Low power
! Industrial & full military temperature ranges
PIN CONFIGURATION (Top View)
FF1 - 1
HF1 - 2
D/R2 - 3
FF2 - 4
HF2 - 5
SEL - 6
EN1 - 7
EN2 - 8
BD15 - 9
BD14 - 10
BD13 - 11
BD12 - 12
BD11 - 13
HI-8582PQI
&
HI-8582PQT
39 - N/C
38 - CWSTR
37 - ENTX
36 - V+
35 - TXBOUT
34 - TXAOUT
33 - V-
32 - FFT
31 - HFT
30 - TX/R
29 - PL2
28 - PL1
27 - BD00
(DS8582 Rev. H)
52 - Pin Plastic Quad Flat Pack (PQFP)
(See page 14 for additional pin configuration)
HOLT INTEGRATED CIRCUITS
1
06/01
1 page  
HI-8582, HI-8583
FUNCTIONAL DESCRIPTION (cont.)
RECEIVER PARITY
The receiver parity circuit counts ones received, including the
parity bit. If the result is odd, then "0" will appear in the 32nd bit.
RETRIEVING DATA
Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). Depending upon the state of control
register bits CR2-CR11, the received ARINC 32-bit word is then
checked for correct decoding and label matching before being
loaded into the 32 x 32 receive FIFO. ARINC words which do not
meet the necessary 9th and 10th ARINC bit or label matching are
ignored and are not loaded into the receive FIFO. The following
table describes this operation.
CR2(3) ARINC word CR6(9) ARINC word
matches
bits 9,10
label
match
CR7,8 (10,11)
0 X0 X
1 No 0
X
1 Yes 0
X
0 X 1 No
0 X 1 Yes
1 Yes 1
No
1 No 1 Yes
1 No 1 No
1 Yes 1 Yes
FIFO
Load FIFO
Ignore data
Load FIFO
Ignore data
Load FIFO
Ignore data
Ignore data
Ignore data
Load FIFO
SEL
MUX
EN CONTROL
TO PINS
32 TO 16 DRIVER
R/W
CONTROL
CONTROL
BITS
HF
FF
D/R
FIFO
LOAD
CONTROL
CONTROL
BIT
32 X 32
FIFO
/ LABEL /
DECODE
COMPARE
CONTROLBITS
CR0, CR14
CLOCK
OPTION
16 x 8
LABEL
MEMORY
EOS
32 BIT SHIFT REGISTER
DATA PARITY
CHECK
BIT CLOCK
32ND
BIT
BIT
COUNTER
AND
END OF
SEQUENCE
ONES
NULL
SHIFT REGISTER
SHIFT REGISTER
WORD GAP
WORD GAP
TIMER
START
SEQUENCE
CONTROL
BIT CLOCK
END
CLOCK
CLK
ZEROS
SHIFT REGISTER
ERROR
DETECTION
ERROR
CLOCK
FIGURE 2. RECEIVER BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
5
5 Page 
HI-8582, HI-8583
Supply Voltages VDD ........................................... -0.3V to +7V Power Dissipation at 25°C
V+ ...................................................... +13.0V
Plastic Quad Flat Pack ..................1.5 W, derate 10mW/°C
V- ...................................................... -13.0V
Ceramic J-LEAD CERQUAD ...... 1.0 W, derate 7mW/°C
Voltage at pins RIN1A, RIN1B, RIN2A, RIN2B ..... -29V to +29V DC Current Drain per pin .............................................. ±10mA
Voltage at any other pin ............................... -0.3V to VDD +0.3V Storage Temperature Range ........................ -65°C to +150°C
Solder temperature (Leads) .................... 280°C for 10 seconds Operating Temperature Range (Industrial): .... -40°C to +85°C
(Package) .......................................... 220°C
(Military): ..... -55°C to +125°C
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
HOLT INTEGRATED CIRCUITS
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet HI-8583.PDF ] | |
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