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PDF AD9444 Data sheet ( Hoja de datos )
| Número de pieza | AD9444 | |
| Descripción | 14-Bit 80 MSPS A/D Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
80 MSPS guaranteed sampling rate
100 dB two-tone SFDR with 69.3 MHz and 70.3 MHz
73.1 dB SNR with 70 MHz input
97 dBc SFDR with 70 MHz input
Excellent linearity
DNL = ±0.4 LSB typical
INL = ±0.6 LSB typical
1.2 W power dissipation
3.3 V and 5 V supply operation
2.0 V p-p differential full-scale input
LVDS outputs (ANSI-644 compatible)
Data format select
Output clock available
APPLICATIONS
Multicarrier, multimode cellular receivers
Antenna array positioning
Power amplifier linearization
Broadband wireless
Radar, infared imaging
Communications instrumentation
GENERAL DESCRIPTION
The AD9444 is a 14-bit monolithic, sampling analog-to-digital
converter (ADC) with an on-chip, track-and-hold circuit and is
optimized for power, small size, and ease of use. The product
operates at up to an 80 MSPS conversion rate and is optimized
w for multicarrier, multimode receivers, such as those found in
cellular infrastructure equipment.
wwThe ADC requires 3.3 V and 5.0 V power supplies and a low
voltage differential input clock for full performance operation.
.DNo external reference or driver components are required for
many applications. Data outputs are LVDS-compatible (ANSI-
a644) or CMOS-compatible and include the means to reduce
tthe overall current needed for short trace distances.
aSheet4Rev. 0
UInformation furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
.infringements of patents or other rights of third parties that may result from its use.
cSpecifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
omregistered trademarks are the property of their respective owners.
14-Bit, 80 MSPS, A/D Converter
AD9444
FUNCTIONAL BLOCK DIAGRAM
AGND AVDD1 AVDD2 DRGND DRVDD
AD9444
VIN+
VIN–
BUFFER
T/H
CLK+
CLK–
CLOCK
AND TIMING
MANAGEMENT
14
PIPELINE
ADC
CMOS
OR
LVDS
OUTPUT
STAGING
2
28
2
REF
DFS
DCS MODE
OUTPUT MODE
OR
D13–D0
DCO
VREF SENSE REFT REFB
Figure 1.
Optional features allow users to implement various selectable
operating conditions, including data format select and output
data mode.
The AD9444 is available in a 100-lead surface-mount plastic
package (100-lead TQFP/EP) specified over the industrial
temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
1. High performance: Outstanding SFDR performance for mul-
ticarrier, multimode 3G and 4G cellular base station
receivers.
2. Ease of use: On-chip reference and track-and-hold. An
output clock simplifies data capture.
3. Packaged in a Pb-free, 100-lead TQFP/EP.
4. Clock DCS maintains overall ADC performance over a wide
range of clock pulse widths.
5. OR (out-of-range) outputs indicate when the signal is beyond
the selected input range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
AD9444
DIGITAL SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, RLVDSBIAS = 3.74 kΩ, unless otherwise noted.
Table 3.
Parameter
CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
DIGITAL OUTPUT BITS—CMOS Mode (D0 to D13, OTR)1
DRVDD = 3.3 V
High Level Output Voltage
Low Level Output Voltage
DIGITAL OUTPUT BITS LVDS Mode (D0 to D13, OTR)
VOD Differential Output Voltage2
VOS Output Offset Voltage
CLOCK INPUTS (CLK+, CLK−)
Differential Input Voltage
Common-Mode Voltage
Differential Input Resistance
Differential Input Capacitance
Temp
Full
Full
Full
Full
Full
Test Level
IV
IV
VI
VI
V
Full IV
Full IV
Full VI
Full VI
Full IV
Full VI
Full V
Full V
AD9444BSVZ-80
Min Typ Max
2.0
−10
2
0.8
+200
+10
Unit
V
V
µA
µA
pF
3.25
247
1.125
0.2
1.3 1.5
8 10
4
V
0.2 V
545
1.375
mV
V
V
1.6 V
12 kΩ
pF
1 Output voltage levels measured with 5 pF load on each output.
2 LVDS RTERM = 100 Ω.
Rev. 0 | Page 5 of 40
5 Page 
AD9444
Table 7. Pin Function Descriptions—100-Lead TQFP/EP in LVDS Mode
Pin No.
Mnemonic Description
Pin No.
1, 8 to 9,
16 to 18,
24 to 27,
34 to 35, 38,
41 to 42, 87,
89 to 95, 98
2 to 4
AVDD1
DNC
5 OUTPUT
MODE
6 DFS
7 LVDSBIAS
10 SENSE
3.3 V (±5%) Analog Supply.
Do Not Connect. These pins
should float.
CMOS Compatible Output Logic
Mode Control Pin. OUTPUT MODE
= 0 for CMOS mode, and OUTPUT
MODE = 1 (AVDD1) for LVDS
outputs.
Data Format Select Pin. CMOS
control pin that determines the
format of the output data. DFS =
high (AVDD1) for twos comple-
ment, DFS = low (ground) for
offset binary format.
Set Pin for LVDS Output Current.
Place 3.7 kΩ resistor terminated to
DRGND.
Reference Mode Selection.
Connect to AGND for internal 1 V
reference, and connect to AVDD2
for external reference.
44
45
46
47, 54, 62,
75, 83
48, 53, 61,
67, 74, 82
49
50
51
52
55
56
57
58
59
60
63
64
65
66
68
69
11 VREF
12, 15, 20,
23, 32, 86,
88, 96 to 97,
99, Exposed
Heat Sink
13
AGND
REFT
1.0 V Reference I/O—Function
Dependent on SENSE. Decouple
to ground with 0.1 µF and 10 µF
capacitors.
Analog Ground. The exposed
heat sink on the bottom of the
package must be connected to
AGND.
Differential Reference Output.
Decoupled to ground with 0.1 µF
capacitor and to REFB (Pin 14) with
0.1 µF and 10 µF capacitors.
70
71
72
73
76
77
78
79
80
81
84
14
REFB
Differential Reference Output.
Decoupled to ground with a 0.1 µF
85
capacitor and to REFT (Pin 13) with
100
0.1 µF and 10 µF capacitors.
19, 28 to 31, AVDD2
39 to 40
5.0 V Analog Supply (±5%).
21
VIN+
Analog Input—True.
22
VIN−
Analog Input—Complement.
33 C1 Internal Bypass Node. Connect a
0.1 µF capacitor from this pin
to AGND.
36
CLK+
Clock Input—True.
37
CLK−
Clock Input—Complement.
43 D0− (LSB) D0 Complement Output Bit
(LVDS Levels).
Mnemonic
D0+
D1−
D1+
DRVDD
DRGND
Description
D0 True Output Bit.
D1 Complement Output Bit.
D1 True Output Bit.
3.3 V Digital Output Supply
(3.0 V to 3.6 V).
Digital Ground.
D2−
D2+
D3−
D3+
D4−
D4+
D5−
D5+
D6−
D6+
DCO−
DCO+
D7−
D7+
D8−
D8+
D9−
D9+
D10−
D10+
D11−
D11+
D12−
D12+
D13−
D13+ (MSB)
OR−
OR+
DCS MODE
D2 Complement Output Bit.
D2 True Output Bit.
D3 Complement Output Bit.
D3 True Output Bit.
D4 Complement Output Bit.
D4 True Output Bit.
D5 Complement Output Bit.
D5 True Output Bit.
D6 Complement Output Bit.
D6 True Output Bit.
Data Clock Output—Complement.
Data Clock Output—True.
D7 Complement Output Bit.
D7 True Output Bit.
D8 Complement Output Bit.
D8 True Output Bit.
D9 Complement Output Bit.
D9 True Output Bit.
D10 Complement Output Bit.
D10 True Output Bit.
D11 Complement Output Bit.
D11 True Output Bit.
D12 Complement Output Bit.
D12 True Output Bit.
D13 Complement Output.
D13 True Output Bit.
Out-of-Range Complement
Output Bit.
Out-of-Range True Output Bit.
Clock Duty Cycle Stabilizer (DCS)
Control Pin, CMOS-Compatible.
DCS = low (AGND) to enable DCS
(recommended). DCS = high
(AVDD1) to disable DCS.
Rev. 0 | Page 11 of 40
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9444.PDF ] | |
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