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PDF SCANSTA101 Data sheet ( Hoja de datos )
| Número de pieza | SCANSTA101 | |
| Descripción | Low Voltage IEEE 1149.1 STA Master | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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October 2002
SCANSTA101
Low Voltage IEEE 1149.1 STA Master
General Description
The SCANSTA101 is designed to function as a test master
for a IEEE 1149.1 test system. The minimal requirements to
create a tester are a microcomputer (uP, RAM/ROM, clock,
etc.), SCANEASE r2.0 software, and a STA101.
The SCANSTA101 is an enhanced version of, and replace-
ment for, the SCANPSC100. The additional features of the
STA101 further allow it to offload some of the processor
overhead while remaining flexible. The device architecture
supports IEEE 1149.1, BIST, and IEEE 1532. The flexibility
will allow it to adapt to any changes that may occur in 1532
and support yet unknown variants.
The SCANSTA101 is useful in improving vector throughput
when applying serial vectors to system test circuitry and
reduces the software overhead that is associated with ap-
plying serial patterns with a parallel processor. The SCAN-
STA101 features a generic Parallel Processor Interface
(PPI) which operates by serializing data from the parallel bus
for shifting through the chain of 1149.1 compliant compo-
nents (i.e., scan chain). Writes can be controlled either by
wait states or the DTACK line. Handshaking is accomplished
with either polling or interrupts.
Features
n Compatible with IEEE Std. 1149.1 (JTAG) Test Access
Port and Boundary Scan Architecture
n Supported by National’s SCAN Ease (Embedded
Application Software Enabler) Software Rev 2.0
n Available as a Silicon Device and Intellectual Property
(IP) model for embedding into VLSI devices
n Uses generic, asynchronous processor interface;
compatible with a wide range of processors and PCLK
frequencies
n 16-bit Data Interface (IP scalable to 32-bit)
n 2Kx32 bit dual-port memory addressing for access by
the PPI or the 1149.1 master
n Load-on-the-fly (LotF) and Preload operating modes
supported
n On-Board Sequencer allows multi-vector operations
such as those required to load data into an FPGA
n On-Board Compares support TDI validation against
preloaded expected data
n 32-bit Linear Feedback Shift Register (LFSR) at the Test
Data In (TDI) port
n State, Shift, and BIST macros allow predetermined TMS
sequences to be utilized
n Operates at 3.3v supply voltages w/ 5V tolerant I/O
n Outputs support Power-Down TRI-STATE mode.
SCANSTA101 Architecture
FIGURE 1.
© 2002 National Semiconductor Corporation DS101215
10121502
www.national.com
1 page  
AC Electrical Characteristics/Operating Requirements Over recommended operating
supply voltage and temperature ranges unless otherwise specified. CL = 50 pF, RL = 500Ω unless otherwise specified.
Symbol
Parameter
Conditions
PARALLEL PROCESSOR INTERFACE (PPI)
tS1 Set Up Time
CE, R/W, Addr, Data to STB
Figures 11, 12
tH1 Hold Time
CE, R/W, Addr, Data to STB
Figures 11, 12
tD1 Propagation Delay
STB low to DTACK low, Register Write
Figure 11
tD1 Propagation Delay
STB low to DTACK low, Register Read
Figure 12
tD1 Propagation Delay
Figure 11
STB low to DTACK low, Memory Write: 16-bit first
access
tD1 Propagation Delay
Figure 11
STB low to DTACK low, Memory Write: 16-bit second
access
tD1 Propagation Delay
Figure 12
STB low to DTACK low, Memory Read: 16-bit first
access
tD1 Propagation Delay
Figure 12
STB low to DTACK low, Memory Read: 16-bit
second access
tD2 Propagation Delay
Figure 11
STB high to DTACK TRISTATE, Register Write
tD2 Propagation Delay
Figure 12
STB high to DTACK TRISTATE, Register Read
tD2 Propagation Delay
Figure 11
STB high to DTACK TRISTATE, Memory Write:
16-bit first access
tD2 Propagation Delay
Figure 11
STB high to DTACK TRISTATE, Memory Write:
16-bit second access
tD2 Propagation Delay
Figure 12
STB high to DTACK TRISTATE, Memory Read:
16-bit first access
tD2 Propagation Delay
Figure 12
STB high to DTACK TRISTATE, Memory Read:
16-bit second access
tD3 Propagation Delay
Figure 12
Output data valid to DTACK low, all read cycles
tpHL1
Propagation Delay
STB low to INT low, register write (clears Interrupt)
Figure 11
tW
fMAX
tRELEASE
Clock Pulse Width, SCK, H or L
Clock Frequency, SCK
Release Time, RST to STB
# of SCK
(Notes 3, 4)
2 or 3
4 or 5
3 or 4
Min Max Units
0 ns
0 ns
11.5
ns
11.5
ns
11.5
ns
7 or 8
11.5
ns
9 or 10
11.5
ns
3 or 4
11.5
ns
1 or 2
1 or 2
1 or 2
10.0
10.0
10.0
ns
ns
ns
1 or 2
10.0
ns
1 or 2
10.0
ns
1 or 2
10.0
ns
1
5 or 6
2
ns
10.5
ns
3.0 ns
66 MHz
ns
Note 3: Due to uncertainty in the relationship of the STB placement to the system clock, SCK, the STB may be detected during the current or the next SCK cycle.
Note 4: An absolute maximum delay can be calculated as: (Max # SCK) x (SCK Period) + tD.
For example, for tD1 (STB low to DTACK low, register write), the # SCK cycles is 2 or 3 and the delay, tD, is 11.5ns. For a SCK with a 100ns period, the absolute
maximum delay is (3 x 100ns) + 11.5, or 311.5ns.
5 www.national.com
5 Page 
Parallel Processor Interface
The overall function of the PPI is to receive the parallel data
from the processor interface, store the data in its appropriate
register or memory location, act on the data if the data are
PPI control data, provide status data back to the processor
and to provide a read path for result data to the processor. To
perform these functions, the PPI consists of seven main
blocks of logic along with the dual-port memory. These
blocks include the Edge Detector (ED), Processor Interface
Controller (PIC), the Memory/ Register Decoder (MRD), the
Word/Long Word Converter (WLWC), the Control Generator
(CG), the Status/Interrupt Generator (SIG) and the Flag
Generator (FG).
WORD/LONG WORD CONVERTER
The Word/Long Word Converter (WLWC) has four 16-bit
capture registers, and least significant/ most significant (LS/
MS) word read capture register pair and an LS/MS word
write capture register pair. Each register within the write
register pair has a separate enable to allow for the neces-
sary control to accomplish word to long word conversions
when in the 16-bit mode. In 32-bit mode, these enables will
be driven simultaneously. A mux is provided in front of the
MS word register for the write capture to select between the
32-bit and 16-bit mode external bus. Only one enable and a
mux select is needed to control the read capture register pair
to accomplish the long word to word conversions when in the
16- bit mode. In the 32-bit mode, the mux selection doesn’t
change so 32-bits are always driven. A mux is on either side
of the LS word register for the read capture. The one at the
register output provides for selection between the 32-bit
and16-bit mode. The one at the register input is for selection
between register space and memory space. All the control
for this block is provided by the PIC and MRD with the 16/32
bit mode enable coming from the Setup register.
EDGE DETECTOR
The PPI module can support either an asynchronous or
synchronous processor interface. For an asynchronous in-
terface the circuit initially synchronizes STB and CE to the
system clock, SCK, by pipelining these two signals through
two flip-flop stages and then performs an edge detection on
STB and CE. For a synchronous parallel processor interface
this circuit just performs an edge detection. The outputs of
this circuit, one clock wide pulses indicating the detection of
negative and positive edges, will be used by the Processor
Interface Controller (PIC) state machine to start and to end a
processor access.
PROCESSOR INTERFACE CONTROLLER
The Processor Interface Controller (PIC) monitors the in-
coming processor control signals and sets up the appropri-
ate internal control signals to move the data into memory or
an internal register on a write or to move the data out of
memory or out of an internal register on a read. The PIC
edge detects the CE and the STB to start the access. The
PIC provides the control for the word to long word conver-
sion in the WLWC by controlling the three enables and the
mux select (READ_MSW) to the capture registers. The PIC
also controls when the internal read/write enable is issued to
the memory to complete the read/write operation. Timing for
register and memory read and write operations is described
in PPI INTERFACE TIMING.
MEMORY/REGISTER DECODER
The Memory/Register Decoder (MRD) contains all six index
registers (Index, Vector Index, Header/Trailer Index, Macro
Index, Sequencer Index and ScanBridge Support Index) and
four address registers (TDI_SM Address, TDO_SM Address,
Expected Address and Mask Address). In general, both in-
dex and address registers are used to maintain pointers to
their respective memory spaces. The exception is the Index
register which is used to set values in the four address
registers, i.e., writing to the Index register sets each of the
address registers. The value written to each address register
is the sum of its base address and the value written to the
Index register (the offset). All index and address registers,
with the exception of the Index register, will auto-increment
with each access to the corresponding memory space.
The MRD provides the address decode to generate all the
control and status register enables for the CG and the SIG.
The MRD also provides the mux selects for the register or
memory selection for the read capture operation in the
WLWC.
CONTROL GENERATOR
The Control Generator has the seven control registers within
it. The Start, Interrupt Control, Setup, Clock Divider, TDI_SM
LFSR Exponent, TDI_SM LFSR LSB Seed, and TDI_SM
LFSR MSB Seed registers are all within this block. The CG
will issue a strobe to the SSI when a write has been issued
to the Start or Setup registers so the SSI can react to the
new control data. The strobe will be derived from edge
detecting the enables to the Start or Setup registers. The
"new" data to the SSI are the Use Sequencer bit and three
Use Vector bits from the Start register, and the TDO Default
Value, TRST, ScanBridge Support Initiate/Release, three
Sync Bit Length, and two Test Loop-back bits from the Setup
register.
STATUS/INTERUPT GENERATOR
The Status/Interrupt Generator has the four status registers
plus the logic to generate the interrupts and clear the inter-
rupts on a read. The registers are the Status, Interrupt
Status, TDI_SM LSFR LSB Result and TDI_SM LFSR MSB
Result registers. The SIG receives the LFSR result and
strobe signal SSI_LFSR_EN from the SSI and captures the
data in the LSB and MSB registers. The SIG receives the
compare result bit value from the SSI along with the com-
pare result bit clear and the compare result bit load.
The SIG receives the 4 memory space flags from the FG
along with their associated load and clear signals so these
bits may be constantly updated. The half-full, half-empty, full
and empty flags will be generated and updated regardless of
the states of their respective interrupt enables. The SIG also
receives the 4 interrupt enables for the flags. The SIG also
receives the sequencer active and 3 vector active signals
from the SSI. These will also be updated regardless of the
enable state.
If an interrupt enable is set then an interrupt will be gener-
ated. If an interrupt occurs at the same time as the interrupt
status is being read, then the interrupt will be set after the
read is complete. All bits in the Interrupt Status register are
cleared when the register is read.
FLAG GENERATOR
The FG takes in the TDI_SM or TDO_SM pointer values
from the PPI address pointers, compares them and gener-
ates the appropriate flags. If a flag condition has occurred, it
is passed along with the corresponding load enable to set
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