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PDF EBD51RC4AAFA Data sheet ( Hoja de datos )
| Número de pieza | EBD51RC4AAFA | |
| Descripción | 512MB Registered DDR SDRAM DIMM | |
| Fabricantes | Elpida Memory | |
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PRELIMINARY DATA SHEET
512MB Registered DDR SDRAM DIMM
EBD51RC4AAFA (64M words × 72 bits, 1 Bank)
Description
The EBD51RC4AAFA is a 64M words × 72 bits × 1
bank Double Data Rate (DDR) SDRAM Module,
mounting 18 pieces of 256Mbits DDR SDRAM sealed
in TSOP package. Read and write operations are
performed at the cross points of the CK and the /CK.
This high-speed data transfer is realized by the 2-bit
prefetch-pipelined architecture. Data strobe (DQS)
both for read and write are available for high speed and
reliable data bus design. By setting extended mode
register, the on-chip Delay Locked Loop (DLL) can be
set enable or disable. This module provides high
density mounting without utilizing surface mount
technology. Decoupling capacitors are mounted
beside each TSOP on the module board.
Features
• 184-pin socket type dual in line memory module
(DIMM)
PCB height: 30.48mm
Lead pitch: 1.27mm
• 2.5V power supply
• Data rate: 266Mbps (max.)
• 2.5 V (SSTL_2 compatible) I/O
• Double Data Rate architecture; two data transfers per
clock cycle
• Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
• Data inputs and outputs are synchronized with DQS
• 4 internal banks for concurrent operation
(Component)
• DQS is edge aligned with data for READs; center
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
referenced to both edges of DQS
• Auto precharge option for each burst access
• Programmable burst length: 2, 4, 8
• Programmable /CAS latency (CL): 3, 3.5
• Refresh cycles: (8192 refresh cycles /64ms)
7.8µs maximum average periodic refresh interval
• 2 variations of refresh
Auto refresh
Self refresh
• 1 piece of PLL clock driver, 2 pieces of register driver
and 1 piece of serial EEPROM (2k bits) for Presence
Detect (SPD) on PCB.
Document No. E0335E10 (Ver. 1.0)
Date Published January 2003 (K) Japan
URL: http://www.elpida.com
Elpida Memory,Inc. 2003
1 page  
EBD51RC4AAFA
Serial PD Matrix*1
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Number of bytes utilized by module
manufacturer
1
0
0
0
0
0
0
0
80H
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08H
Memory type
0 0 0 0 0 1 1 1 07H
Number of row address
0 0 0 0 1 1 0 1 0DH
Number of column address
0 0 0 0 1 0 1 1 0BH
Number of DIMM banks
0 0 0 0 0 0 0 1 01H
Module data width
0 1 0 0 1 0 0 0 48H
Module data width continuation
0 0 0 0 0 0 0 0 00H
Voltage interface level of this assembly 0 0 0 0 0 1 0 0 04H
DDR SDRAM cycle time, CL = X
-7A
0 1 1 1 0 0 0 0 70H
-7B 0 1 1 1 0 1 0 1 75H
SDRAM access from clock (tAC)
0 1 1 1 0 1 0 1 75H
DIMM configuration type
0 0 0 0 0 0 1 0 02H
12 Refresh rate/type
1 0 0 0 0 0 1 0 82H
13 Primary SDRAM width
0 0 0 0 0 1 0 0 04H
14 Error checking SDRAM width
0 0 0 0 0 1 0 0 04H
SDRAM device attributes:
15 Minimum clock delay back-to-back 0 0 0 0 0 0 0 1 01H
column access
16
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 1 0 0EH
17
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04H
18
SDRAM device attributes:
/CAS latency
0 0 0 0 1 1 0 0 0CH
19
SDRAM device attributes:
/CS latency
20
SDRAM device attributes:
/WE latency
0 0 0 0 0 0 0 1 01H
0 0 0 0 0 0 1 0 02H
21 SDRAM module attributes
0 0 1 0 0 1 1 0 26H
22 SDRAM device attributes: General 1 1 0 0 0 0 0 0 C0H
Minimum clock cycle time at
23 CLX - 0.5
-7A
0 1 1 1 0 1 0 1 75H
-7B 1 0 1 0 0 0 0 0 A0H
24
Maximum data access time (tAC) from
clock at CLX - 0.5
0
1
1
1
0
1
0
1
75H
25
Minimum clock cycle time at
CLX - 1
0 0 0 0 0 0 0 0 00H
26
Maximum data access time (tAC) from
clock at CLX - 1
0
0
0
0
0
0
0
0
00H
27 Minimum row precharge time (tRP) 0 1 0 1 0 0 0 0 50H
28
Minimum row active to row active
delay (tRRD)
0 0 1 1 1 1 0 0 3CH
29 Minimum /RAS to /CAS delay (tRCD) 0 1 0 1 0 0 0 0 50H
30
Minimum active to precharge time
(tRAS)
0 0 1 0 1 1 0 1 2DH
Comments
128
256 byte
SDRAM DDR
13
11
1
72 bits
0 (+)
SSTL 2.5V
CL = 2.5*3
0.75ns*3
ECC
7.8 µs
Self refresh
×4
×4
1 CLK
2, 4, 8
4
2/2.5
0
1
Registered
± 0.2V
CL = 2*3
0.75ns*3
20ns
15ns
20ns
45ns
Preliminary Data Sheet E0335E10 (Ver. 1.0)
5
5 Page 
EBD51RC4AAFA
DC Characteristics 1 (TA = 0 to 70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)
Parameter
Symbol Grade
max.
Unit Test condition
Notes
Operating current (ACTV-PRE) IDD0
Operating current
(ACTV-READ-PRE)
IDD1
Idle power down standby current IDD2P
Floating idle standby current
Active power down standby
current
Active standby current
Operating current
(Burst read operation)
Operating current
(Burst write operation)
Auto refresh current
IDD2F
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
Self refresh current
Random read current
(4 banks interleaving)
IDD6
IDD7
-7A
-7B
-7A
-7B
-7A
-7B
-7A
-7B
-7A
-7B
-7A
-7B
-7A
-7B
-7A
-7B
-7A
-7B
-7A
-7B
-7A
-7B
2194
2096
3184
2996
718
656
1114
1016
844
746
1294
1196
4444
4256
4084
3896
4084
3986
448
440
6326
6146
mA
CKE ≥ VIH,
tRC = tRC (min.)
1, 2, 5
CKE ≥ VIH, BL = 2,
mA CL = 3.5,
1, 2, 5
tRC = tRC (min.)
mA CKE ≤ VIL
4
mA CKE ≥ VIH, /CS ≥ VIH 4
mA CKE ≤ VIL
3
mA
CKE ≥ VIH, /CS ≥ VIH,
tRAS = tRAS (max.)
3
mA
CKE ≥ VIH, BL = 2,
CL = 3.5
1, 2, 5, 6
mA
CKE ≥ VIH, BL = 2,
CL = 3.5
1, 2, 5, 6
mA
tRFC = tRFC (min.),
Input ≤ VIL or ≥ VIH
mA
Input ≥ VDD – 0.2V
Input ≤ 0.2V.
mA BL = 4
5, 6, 8
Notes. 1. These IDD data are measured under condition that DQ pins are not connected.
2. One bank operation.
3. One bank active.
4. All banks idle.
5. Command/Address transition once per one cycle.
6. Data/Data mask transition twice per one cycle.
7. The IDD data on this table are measured with regard to tCK = min. in general.
8. 4 banks active. Only one bank is running at tRC = tRC (min.)
DC Characteristics 2 (TA = 0 to 70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)
(DDR SDRAM Component Specification)
Parameter
Symbol
min.
max.
Unit Test condition
Input leakage current
Output leakage current
Output high current
Output low current
ILI
ILO
IOH
IOL
–10
–10
–16.8
16.8
10
10
—
—
µA VDD ≥ VIN ≥ VSS
µA VDD ≥ VOUT ≥ VSS
mA VOUT = VTT + 0.84V
mA VOUT = VTT – 0.84V
Notes
Preliminary Data Sheet E0335E10 (Ver. 1.0)
11
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| PDF Descargar | [ Datasheet EBD51RC4AAFA.PDF ] | |
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