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PDF EBD52UD6ADSA Data sheet ( Hoja de datos )
| Número de pieza | EBD52UD6ADSA | |
| Descripción | 512MB DDR SDRAM SO-DIMM | |
| Fabricantes | Elpida Memory | |
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DATA SHEET
512MB DDR SDRAM SO-DIMM
EBD52UD6ADSA (64M words × 64 bits, 2 Ranks)
Description
The EBD52UD6ADSA is 64M words × 64 bits, 2 ranks
Double Data Rate (DDR) SDRAM Small Outline Dual
In-line Memory Module, mounting 8 pieces of 512M
bits DDR SDRAM sealed in TSOP package. Read and
write operations are performed at the cross points of
the CK and the /CK. This high-speed data transfer is
realized by the 2 bits prefetch-pipelined architecture.
Data strobe (DQS) both for read and write are available
for high speed and reliable data bus design. By setting
extended mode register, the on-chip Delay Locked
Loop (DLL) can be set enable or disable. This module
provides high density mounting without utilizing surface
mount technology. Decoupling capacitors are mounted
beside each TSOP on the module board.
Features
• 200-pin socket type small outline dual in line memory
module (SO-DIMM)
PCB height: 31.75mm
Lead pitch: 0.6mm
• 2.5V power supply
• Data rate: 333Mbps/266Mbps (max.)
• 2.5 V (SSTL_2 compatible) I/O
• Double Data Rate architecture; two data transfers per
clock cycle
• Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
• Data inputs, outputs and DM are synchronized with
DQS
• 4 internal banks for concurrent operation
(Component)
• DQS is edge aligned with data for READs; center
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
referenced to both edges of DQS
• Data mask (DM) for write data
• Auto precharge option for each burst access
• Programmable burst length: 2, 4, 8
• Programmable /CAS latency (CL): 2, 2.5
• Refresh cycles: (8192 refresh cycles /64ms)
7.8µs maximum average periodic refresh interval
• 2 variations of refresh
Auto refresh
Self refresh
Document No. E0425E30 (Ver. 3.0)
Date Published January 2004 (K) Japan
URL: http://www.elpida.com
Elpida Memory , Inc. 2003-2004
1 page  
EBD52UD6ADSA
Serial PD Matrix
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
0
Number of bytes utilized by module
manufacturer
1 0 0 0 0 0 0 0 80H
1
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08H
2 Memory type
0 0 0 0 0 1 1 1 07H
3 Number of row address
0 0 0 0 1 1 0 1 0DH
4 Number of column address
0 0 0 0 1 0 1 0 0AH
5 Number of DIMM ranks
0 0 0 0 0 0 1 0 02H
6 Module data width
0 1 0 0 0 0 0 0 40H
7 Module data width continuation
0 0 0 0 0 0 0 0 00H
8 Voltage interface level of this assembly 0 0 0 0 0 1 0 0 04H
9
DDR SDRAM cycle time, CL = X
-6B
0 1 1 0 0 0 0 0 60H
-7A, -7B
0 1 1 1 0 1 0 1 75H
10
SDRAM access from clock (tAC)
-6B
-7A, -7B
0 1 1 1 0 0 0 0 70H
0 1 1 1 0 1 0 1 75H
11 DIMM configuration type
0 0 0 0 0 0 0 0 00H
12 Refresh rate/type
1 0 0 0 0 0 1 0 82H
13 Primary SDRAM width
0 0 0 1 0 0 0 0 10H
14 Error checking SDRAM width
0 0 0 0 0 0 0 0 00H
SDRAM device attributes:
15
Minimum clock delay back-to-back
0 0 0 0 0 0 0 1 01H
column access
16
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 1 0 0EH
17
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04H
18 SDRAM device attributes: /CAS latency 0 0 0 0 1 1 0 0 0CH
19 SDRAM device attributes: /CS latency 0 0 0 0 0 0 0 1 01H
20 SDRAM device attributes: /WE latency 0 0 0 0 0 0 1 0 02H
21 SDRAM module attributes
0 0 1 0 0 0 0 0 20H
22
SDRAM device attributes: General
1 1 0 0 0 0 0 0 C0H
Minimum clock cycle time at
23 CL = X –0.5
-6B, -7A
0 1 1 1 0 1 0 1 75H
-7B 1 0 1 0 0 0 0 0 A0H
Maximum data access time (tAC) from
24 clock at CL = X –0.5
0 1 1 1 0 0 0 0 70H
-6B
-7A, -7B
0 1 1 1 0 1 0 1 75H
25 to 26
0 0 0 0 0 0 0 0 00H
27
Minimum row precharge time (tRP)
-6B
0 1 0 0 1 0 0 0 48H
-7A, -7B
0 1 0 1 0 0 0 0 50H
Minimum row active to row active delay
28 (tRRD)
0 0 1 1 0 0 0 0 30H
-6B
-7A, -7B
0 0 1 1 1 1 0 0 3CH
Comments
128 bytes
256 bytes
DDR SDRAM
13
10
2
64 bits
0
SSTL2
CL = 2.5*1
0.7ns*1
0.75ns*1
None
7.8µs
Self refresh
× 16
Not used
1 CLK
2,4,8
4
2, 2.5
0
1
Unbuffered
VDD ± 0.2V
CL = 2*1
0.7ns*1
0.75ns*1
18ns
20ns
12ns
15ns
Data Sheet E0425E30 (Ver. 3.0)
5
5 Page 
EBD52UD6ADSA
DC Characteristics 1 (TA = 0 to +70°C, VDD = 2.5V ± 0.2V, VSS = 0V)
Parameter
Symbol
Grade
max.
Unit Test condition
Notes
Operating current (ACTV-PRE)
Operating current
(ACTV-READ-PRE)
IDD0
IDD1
-6B
-7A, -7B
-6B
-7A, -7B
860
760
1100
940
mA
CKE ≥ VIH,
tRC = tRC (min.)
1, 2, 9
CKE ≥ VIH, BL = 4,
mA CL = 2.5,
1, 2, 5
tRC = tRC (min.)
Idle power down standby current IDD2P
24
mA CKE ≤ VIL
4
Floating idle standby current
Quiet idle standby current
Active power down
standby current
Active standby current
Operating current
(Burst read operation)
Operating current
(Burst write operation)
Auto refresh current
Self refresh current
Operating current
(4 banks interleaving)
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7A
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
240
200
160
160
520
440
1340
1140
1340
1140
1540
1420
32
2380
2020
mA
CKE ≥ VIH, /CS ≥ VIH,
DQ, DQS, DM = VREF
4, 5
mA
CKE ≥ VIH, /CS ≥ VIH,
DQ, DQS, DM = VREF
4, 10
mA CKE ≤ VIL
3
mA
CKE ≥ VIH, /CS ≥ VIH
tRAS = tRAS (max.)
3, 5, 6
mA
CKE ≥ VIH, BL = 2,
CL = 2.5
1, 2, 5, 6
mA
CKE ≥ VIH, BL = 2,
CL = 2.5
1, 2, 5, 6
mA
tRFC = tRFC (min.),
Input ≤ VIL or ≥ VIH
mA
Input ≥ VDD – 0.2 V
Input ≤ 0.2 V
mA BL = 4
1, 5, 6, 7
Notes. 1. These IDD data are measured under condition that DQ pins are not connected.
2. One bank operation.
3. One bank active.
4. All banks idle.
5. Command/Address transition once per one cycle.
6. DQ, DM, DQS transition twice per one cycle.
7. 4 banks active. Only one bank is running at tRC = tRC (min.)
8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.
9. Command/Address transition once every two clock cycles.
10. Command/Address stable at ≥ VIH or ≤ VIL.
DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)
Parameter
Symbol
min.
max.
Unit Test condition
Input leakage current
ILI
–16
Output leakage current
ILO
–10
Output high current IOH –15.2
Output low current IOL 15.2
Note: 1. DDR SDRAM component specification.
16
10
—
—
µA VDD ≥ VIN ≥ VSS
µA VDD ≥ VOUT ≥ VSS
mA VOUT = 1.95V
mA VOUT = 0.35V
Notes
1
1
Data Sheet E0425E30 (Ver. 3.0)
11
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