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PDF WEDPN4M72V Data sheet ( Hoja de datos )
| Número de pieza | WEDPN4M72V | |
| Descripción | 4M x 72 SDRAM | |
| Fabricantes | White Electronic Designs | |
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White Electronic Designs
WEDPN4M72V-XBX
4Mx72 Synchronous DRAM*
FEATURES
High Frequency = 100, 125MHz
Package:
* 219 Plastic Ball Grid Array (PBGA), 25 x 21mm
D Single 3.3V ±0.3V power supply
Fully Synchronous; all signals registered on positive
Eedge of system clock cycle
Internal pipelined operation; column address can be
Dchanged every clock cycle
Internal banks for hiding row access/precharge
N Programmable Burst length 1,2,4,8 or full page
E 4096 refresh cycles
Commercial, Industrial and Military Temperature
Ranges
M Organized as 4M x 72
Weight: WEDPN4M72V-XBX - 2 grams typical
MBENEFITS
O 60% SPACE SAVINGS
C Reduced part count
Reduced I/O count
E 19% I/O Reduction
w Lower inductance and capacitance for low noise
w Rperformance
Suitable for hi-reliability applications
w T Upgradeable to 8M x 72 density with same footprint
(contact factory for information)
.DO* This product is Not Recommended for New Designs, refer to WEDPN4M72V-XB2X
for new designs.
GENERAL DESCRIPTION
The 32MByte (256Mb) SDRAM is a high-speed CMOS,
dynamic random-access ,memory using 5 chips containing
67,108,864 bits. Each chip is internally configured as a
quad-bank DRAM with a synchronous interface. Each of
the chip’s 16,777,216-bit banks is organized as 4,096 rows
by 256 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0, BA1 select the bank; A0-
11 select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page, with
a burst terminate option. An AUTO PRECHARGE function
may be enabled to provide a self-timed row precharge that
is initiated at the end of the burst sequence.
The 256Mb SDRAM uses an internal pipelined architecture
to achieve high-speed operation. This architecture is
compatible with the 2n rule of prefetch architectures, but
it also allows the column address to be changed on every
clock cycle to achieve a high-speed, fully random access.
Precharging one bank while accessing one of the other
three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
Nata Discrete Approach
S 11.9 11.9 11.9 11.9
11.9
he54
e22.3 TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
t4UArea
5 x 265mm2 = 1328mm 2
.cI/O
oCount
5 x 54 pins = 270 pins
mWhite Electronic Designs Corp. reserves the right to change products or specifications without notice.
ACTUAL SIZE
White Electronic Designs
WEDPN4M72V-XBX
21
25
S
A
V
I
N
G
S
525mm 2
60%
219 Balls 19%
April, 2004
Rev. 15
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page  
White Electronic Designs
WEDPN4M72V-XBX
FIG. 2 MODE REGISTER DEFINITION
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
Reserved* WB Op Mode CAS Latency BT Burst Length
Mode Register (Mx)
*Should program
M11, M10 = 0, 0
to ensure compatibility
with future devices.
M2 M1M0
0 00
0 01
0 10
0 11
1 00
1 01
1 10
1 11
Burst Length
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
M3
0
1
M6 M5 M4
0 00
0 01
0 10
0 11
1 00
1 01
1 10
1 11
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
M8
M7
M6-M0
Operating Mode
0
0
Defined
Standard Operation
--
- All other states reserved
M9 Write Burst Mode
0 Programmed Burst Length
1 Single Location Access
TABLE 1 - BURST DEFINITION
Burst
Length
2
4
8
Full
Page
(y)
Starting Column
Address
A1
0
0
1
1
A2 A1
00
00
01
01
10
10
11
11
A0
0
1
A0
0
1
0
1
A0
0
1
0
1
0
1
0
1
n = A 0-9/8/7
(location 0-y)
Order of Accesses Within a Burst
Type = Sequential Type = Interleaved
0-1 0-1
1-0 1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
…Cn - 1,
Cn…
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not Supported
NOTES:
1. For full-page accesses: y = 256.
2. For a burst length of two, A1-7 select the block-of-two burst; A0 selects the
starting column within the block.
3. For a burst length of four, A2-7 select the block-of-four burst; A0-1 select the
starting column within the block.
4. For a burst length of eight, A3-7 select the block-of-eight burst; A0-2 select the
starting column within the block.
5. For a full-page burst, the full row is selected and A0-7 select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the
following access wraps within the block.
7. For a burst length of one, A0-7 select the unique column to be accessed, and
Mode Register bit M3 is ignored.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April, 2004
Rev. 15
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
5 Page 
White Electronic Designs
WEDPN4M72V-XBX
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS
(NOTES 5, 6, 8, 9, 11)
Parameter
Access time from CK (pos. edge)
Address hold time
Address setup time
CL = 3
CL = 2
CK high-level width
CK low-level width
Clock cycle time (22)
CL = 3
CL = 2
CKE hold time
CKE setup time
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
Data-in setup time
Data-out high-impedance time
CL = 3 (10)
CL = 2 (10)
Data-out low-impedance time
Data-out hold time (load)
Data-out hold time (no load) (26)
ACTIVE to PRECHARGE command
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
Refresh period (4,096 rows) – Commercial, Industrial
Refresh period (4,096 rows) – Military
AUTO REFRESH period
PRECHARGE command period
ACTIVE bank A to ACTIVE bank B command
Transition time (7)
WRITE recovery time
(23)
(24)
Exit SELF REFRESH to ACTIVE command
Symbol
tAC
tAC
tAH
tAS
tCH
tCL
tCK
tCK
tCKH
tCKS
tCMH
tCMS
tDH
tDS
tHZ
tHZ
tLZ
tOH
tOHN
tRAS
tRC
tRCD
tREF
tREF
tRFC
tRP
tRRD
tT
tWR
tXSR
-100
Min Max
7
7
1
2
3
3
10
13
1
2
1
2
1
2
1
3
1.8
50
70
20
70
20
15
0.3
1 CK + 7ns
15
80
7
7
120,000
64
16
1.2
-125
Min Max
6
6
1
2
3
3
8
10
1
2
1
2
1
2
1
3
1.8
45
70
21
70
20
15
0.3
1 CK + 7ns
14
78
6
6
120,000
64
16
1.2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
—
ns
ns
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April, 2004
Rev. 15
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
11 Page | ||
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| PDF Descargar | [ Datasheet WEDPN4M72V.PDF ] | |
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