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PDF KM718V887 Data sheet ( Hoja de datos )
| Número de pieza | KM718V887 | |
| Descripción | 256Kx18 Synchronous SRAM | |
| Fabricantes | Samsung semiconductor | |
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KM718V887
256Kx18 Synchronous SRAM
Document Title
256Kx18-Bit Synchronous Burst SRAM
Revision History
Rev. No. History
Draft Date
Remark
0.0 Initial draft
May. 15. 1997
Preliminary
0.1 Modify power down cycle timing & Interleaved read timing,
Insert Note 4 at AC timing characteristics.
Change ISB1 value from 10mA to 30mA.
Change ISB2 value from 10mA to 20mA.
February. 11. 1998 Preliminary
0.2 Change Undershoot spec
from -3.0V(pulse width≤20ns) to -2.0V(pulse width≤tCYC/2)
Add Overshoot spec 4.6V((pulse width≤tCYC/2)
Change VIH max from 5.5V to VDD+0.5V
April. 14. 1998
0.3 Change ISB2 value from 20mA to 30mA.
May 13. 1998
Change VDD condition from VDD=3.3V+10%/-5% to VDD=3.3V+0.3V/-0.165V.
1.0 Final spec Release
May 15. 1998
Preliminary
Preliminary
Final
2.0 Add VDDQ Supply voltage( 2.5V )
Dec. 02. 1998
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
- 1 - December 1998
Rev. 2.0
1 page  
KM718V887
256Kx18 Synchronous SRAM
SYNCHRONOUS TRUTH TABLE
CS1 CS2 CS2 ADSP ADSC ADV WRITE CLK
HXXXLX X ↑
L LXLXX X ↑
ADDRESS ACCESSED
None
None
LXHLXX X ↑
None
LLXXLX X ↑
None
LXHXLX X ↑
None
LHL LXX X ↑
LHLHLX L ↑
LHLHLX H ↑
XXXHHL H ↑
HXXXHL H ↑
XXXHHL L ↑
HXXXHL L ↑
XXXHHH H ↑
HXXXHH H ↑
XXXHHH L ↑
HXXXHH L ↑
External Address
External Address
External Address
Next Address
Next Address
Next Address
Next Address
Current Address
Current Address
Current Address
Current Address
Notes : 1. X means "Don′t Care".
2. The rising edge of clock is symbolized by ↑.
3. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
OPERATION
Not Selected
Not Selected
Not Selected
Not Selected
Not Selected
Begin Burst Read Cycle
Begin Burst Write Cycle
Begin Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Write Cycle
Continue Burst Write Cycle
Suspend Burst Read Cycle
Suspend Burst Read Cycle
Suspend Burst Write Cycle
Suspend Burst Write Cycle
WRITE TRUTH TABLE
GW
BW
WEa
WEb
HHXX
H L HH
HL LH
HLHL
HL L L
LXXX
Notes : 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).
OPERATION
READ
READ
WRITE BYTE a
WRITE BYTE b
WRITE ALL BYTEs
WRITE ALL BYTEs
- 5 - December 1998
Rev. 2.0
5 Page 
KM718V887
256Kx18 Synchronous SRAM
- 11
December 1998
Rev. 2.0
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet KM718V887.PDF ] | |
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