ICS9250-23 Datasheet PDF - Integrated Circuit Systems
| Part Number | ICS9250-23 | |
| Description | Frequency Generator & Integrated Buffers for Celeron & PII/III | |
| Manufacturers | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
ICS9250-23
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
810/810E type chipset
Output Features:
• 2 - CPUs @ 2.5V, up to 166MHz.
• 13 - SDRAM @ 3.3V, up to 166MHz.
• 2 - 3V66 @ 3.3V, 2x PCI MHz.
• 8 - PCI @3.3V.
• 1 - 48MHz, @3.3V fixed.
• 1 - 24MHz @ 3.3V
• 2 - REF @3.3V, 14.318MHz.
Features:
• Up to 166MHz frequency support
• Support power management through PD#.
• Spread spectrum for EMI control (± 0.25%)
center spread.
• Uses external 14.318MHz crystal
• FS pins for frequency select
Key Specifications:
• CPU Output Jitter: <250ps
• IOAPIC Output Jitter: <500ps
• 48MHz, 3V66, PCI Output Jitter: <500ps
• Ref Output Jitter. <1000ps
• CPU Output Skew: <175ps
• PCI Output Skew: <500ps
• 3V66 Output Skew <175ps
• For group skew timing, please refer to the
Group Timing Relationship Table.
Pin Configuration
56-Pin 300 mil SSOP
1. These pins will have 2X drive strength.
* 120K ohm pull-up to VDD on indicated inputs.
Block Diagram
Power Groups
GNDREF, VDDREF = REF, Crystal
GND3V66, VDD3V66 = 3V66
GNDPCI, VDDPCI = PCICLKs
GNDCOR, VDDCOR = PLLCORE
GND48, VDD48 = 48
GNDSDR, VDDSDR = SDRAM
GNDLCPU, VDDLCPU = CPUCLK
GNDLPCI, VDDLAPIC = IOAPIC
9250-23 Rev A 4/3/01
Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
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ICS9250-23
Shared Pin Operation -
Input/Output Pins
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used both to provide the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. When no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, then
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
Programming
Header
Via to Gnd
Via to
VDD
2K W
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
Third party brands and names are the property of their respective owners.
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| Information | Total 15 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ ICS9250-23.PDF Datasheet ] | |
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