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PDF UDA1380 Data sheet ( Hoja de datos )
| Número de pieza | UDA1380 | |
| Descripción | Stereo audio coder-decoder for MD / CD and MP3 | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
UDA1380
Stereo audio coder-decoder
for MD, CD and MP3
Product specification
2002 Sep 16
1 page  
Philips Semiconductors
Stereo audio coder-decoder
for MD, CD and MP3
Product specification
UDA1380
4 QUICK REFERENCE DATA
VDDD = VDDA(AD) = VDDA(DA) = VDDA(HP) = 3.0 V; Tamb = 25 °C; RL = 5 kΩ; all voltages measured with respect to ground;
unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Supplies
VDDA(AD)
VDDA(DA)
VDDA(HP)
VDDD
IDDA(AD)
IDDA(DA)
IDDA(HP)
IDDD
IDD(tot)
Tamb
ADC analog supply voltage
DAC analog supply voltage
headphone analog supply
voltage
digital supply voltage
ADC analog supply current
DAC analog supply current
headphone analog supply
current
digital supply current
total supply current
ambient temperature
2.4
2.4
2.4
one ADC and microphone amplifier
enabled; fs = 48 kHz
two ADCs and PGA enabled;
fs = 48 kHz
all ADCs and PGAs power-down, but
AVC activated; fs = 48 kHz
all ADCs, PGAs and LNA
power-down; fs = 48 kHz
operating mode; fs = 48 kHz
Power-down mode; fs = 48 kHz
no signal applied (quiescent current)
Power-down mode
operating mode; fs = 48 kHz
playback mode; fs = 48 kHz
record mode; fs = 48 kHz
Power-down mode; fs = 48 kHz
playback mode (without headphone);
fs = 48 kHz
playback mode (with headphone); no
signal; fs = 48 kHz
record mode (audio); fs = 48 kHz
record mode (speech); fs = 48 kHz
record mode (audio and speech);
fs = 48 kHz
fully operating; fs = 48 kHz
signal mix-in operating, using
FSDAC, AVC (with headphone); no
signal; fs = 48 kHz
Power-down mode; fs = 48 kHz
2.4
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−40
3.0 3.6
3.0 3.6
3.0 3.6
3.0 3.6
4.5 −
7.0 −
3.3 −
1.0 −
3.4 −
0.1 −
0.9 −
0.1 −
10.0 −
5.0 −
6.0 −
1.0 −
9.0 −
8.8 −
13.0 −
10.0 −
13.0 −
23.0 −
12.0 −
2.0 −
− +85
V
V
V
V
mA
mA
mA
µA
mA
µA
mA
µA
mA
mA
mA
µA
mA
mA
mA
mA
mA
mA
mA
µA
°C
2002 Sep 16
5
5 Page 
Philips Semiconductors
Stereo audio coder-decoder
for MD, CD and MP3
Product specification
UDA1380
8 FUNCTIONAL DESCRIPTION
8.1 Clock modes
There are two clock systems:
• A SYSCLK signal, coming from the system or the SSA1
chip
• A WSPLL which generates the internal clocks from the
incoming WSI signal.
The system frequency applied to pin SYSCLK is
selectable. The options are 256fs, 384fs, 512fs and 768fs.
The system clock must be locked in frequency to the digital
interface signals.
Remark: Since there is neither a fixed reference clock
available in the IC itself, nor a fixed clock available in the
system the IC is in, there is no auto sample rate conversion
detection circuitry.
The system can run in several modes, using the two clock
systems:
• Both the DAC and the ADC part can run at the applied
SYSCLK input. In this case the WSPLL is
powered-down
• The ADC can run at the SYSCLK input, and at the same
time the DAC part can run (at a different frequency) at
the clock re-generated from the WSI signal
• The ADC and the DAC can both run at the clock
regenerated from the WSI signal.
8.1.1 WSPLL REQUIREMENTS
The WSPLL is meant to lock onto the WSI input signal, and
regenerates a 256fs and 128fs signal for the FSDAC and
the interpolator core (and for the decimator if needed).
Since the operating range of the WSPLL is from
75 to 150 MHz, the complete range of 8 to 100 kHz
sampling frequency must be divided into smaller parts, as
given in Table 1, using Fig.4 as a reference. This means
that the user must set the input range of the WSI input
signal.
In case the SYSCLK is used for clocking the complete
system (decimator including interpolator) the WSPLL must
be powered-down with bit ADC_CLK via the L3-bus
or I2C-bus.
The SEL_LOOP_DIV[1:0] can be controlled by the PLL1
and PLL0 bits in the L3-bus or I2C-bus register.
handbook, halfpage
WSI
VCO
DIV1
PRE1
128fs
(digital parts)
256fs
(ADC and FSDAC)
MGU527
Fig.4 WSPLL set-up.
Table 1 WSPLL divider settings
WORD SELECT
FREQUENCY (kHz)
6.25 to 12.5
12.5 to 25
25 to 50
50 to 100
SEL_LOOP_DIV[1:0]
00
01
10
11
PRE1
8
4
2
2
DIV1
1 536
1 536
1 536
768
VCO FREQUENCY
(MHz)
76 to 153
2002 Sep 16
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet UDA1380.PDF ] | |
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