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IN74ACT112 fiches techniques PDF

IK Semiconductor - Dual J-K Negative-Edge-Triggered Flip-Flop

Numéro de référence IN74ACT112
Description Dual J-K Negative-Edge-Triggered Flip-Flop
Fabricant IK Semiconductor 
Logo IK Semiconductor 





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IN74ACT112 fiche technique
TECHNICAL DATA
Dual J-K Flip-Flop
with Set and Reset
High-Speed Silicon-Gate CMOS
IN74ACT112
The IN74ACT112 is identical in pinout to the LS/ALS112,
HC/HCT112. The IN74ACT112 may be used as a level converter for
interfacing TTL or NMOS outputs to High Speed CMOS inputs.
Each flip-flop is negative-edge clocked and has active-low
asynchronous Set and Reset inputs.
TTL/NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 µA; 0.1 µA @ 25°C
Outputs Source/Sink 24 mA
ORDERING INFORMATION
IN74ACT112N Plastic
IN74ACT112D SOIC
TA = -40° to 85° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
www.datasheetPP4IINNu81.=6c=GVoNCDCm
FUNCTION TABLE
Inputs
Outputs
Set Reset Clock J K Q
Q
LH
X XX H L
HL
LL
X XX L H
X X X L* L*
HH
L L No Change
HH
LH L
H
HH
HL H
L
HH
HH
Toggle
HH
L X X No Change
HH
H X X No Change
HH
X X No Change
* Both outputs will remain low as long as Set and Reset are
low, but the output states are unpredictable if Set and Reset
go high simultaneously
X = Don’t Care
1

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