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PDF IN74HC323A Data sheet ( Hoja de datos )
| Número de pieza | IN74HC323A | |
| Descripción | 8-Bit Universal Shift/Storage Register | |
| Fabricantes | IK Semiconductor | |
| Logotipo |  |
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TECHNICAL DATA
8-Bit Bidirectional Universal
Shift Register with Parallel I/O
High-Performance Silicon-Gate CMOS
IN74HC323A
The IN74HC323A is identical in pinout to the LS/ALS323. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
The IN74HC323A features a multiplexed parallel input/output data
port to active full 8-bit handling in a 20 pin package. Due to the large
output drive capability and the 3-state feature, this device is ideally suited
for interface with bus lines in a bus-oriented system.
Two Mode-Select inputs and two Output Enable inputs are used to
choose the mode of operation as listed in the Function Table.
Synchronous parallel loading is accomplished by taking both Mode-
Select lines, S1 and S2, high. This places the outputs in the high-
impedance state, which permits data applied to the data port to be clocked
into the register. Reading out of the register can be accomplished when
the outputs are enabled. The active-low synchronous Reset overrides all
other inputs.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
IN74HC323AN Plastic
IN74HC323ADW SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
www.datasheet4u.coPmPININ1020==GVNCCD
1
1 page  
IN74HC323A
TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns)
VCC Guaranteed Limit
Symbol
Parameter
V 25 °C to-55°C ≤85°C ≤125°C
tsu Minimum Setup Time, Mode Select 2.0
S1 or S2 to Clock (Figure 4)
4.5
6.0
100
20
17
125 150
25 30
21 26
tsu Minimum Setup Time, Data Inputs
SA, SH, PA thru PH to Clock
(Figure 4)
2.0
4.5
6.0
100
20
17
125 150
25 30
21 26
th Minimum Hold Time, Clock to Mode 2.0
Select S1 or S2 (Figure 4)
4.5
6.0
120
24
20
150 180
30 36
26 31
th Minimum Hold Time, Clock to Data 2.0
Inputs, SA, SH, PA thru PH (Figure 4) 4.5
6.0
5
5
5
55
55
55
tw Minimum Pulse Width, Clock
(Figure 1)
2.0 80
4.5 16
6.0 14
100 120
20 24
17 20
tw Minimum Pulse Width, Reset (Figure 2.0
2) 4.5
6.0
80
16
14
100 120
20 24
17 20
tr, tf Maximum Input Rise and Fall Times 2.0
(Figure 1)
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
Unit
ns
ns
ns
ns
ns
ns
ns
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet IN74HC323A.PDF ] | |
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