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PDF SC680E Data sheet ( Hoja de datos )

Número de pieza SC680E
Descripción SMBus System Clock Buffer
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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APPROVED PRODUCT
SC680E
SMBus System Clock Buffer
Product Features
§ 18 output buffer for high clock fanout applications
§ Each output can be internally disabled for EMI
reduction
§ VDD=3.3 volts for chip Vdd
§ Output frequency range 10 Mhz to 100 Mhz
§ < 250ps skew between output clocks
§ 48-pin SSOP package
§ Single Clock Enable pin for testability
Block Diagram
REFIN
OE
SDATA
SCLK
Control
Logic
VDD
CLK[1:2]
VDD
CLK[3:4]
VDD
CLK[5:6]
VDD
CLK[7:8]
VDD
CLK[9:10]
VDD
CLK[11:12]
VDD
CLK[13:14]
VDD
CLK[15:16]
VDD
CLK[17,18]
tasheet4u.comCypress Semiconductor Corporation
a3901 North First St.
.dSan Jose, CA 95134. Tel: 408-943-2600
wwwhttp://www.cypress.com
Product Description
The SC680 is a high fanout system clock buffer. Its
primary application is to create the large quantity of
clocks needed to support a wide range of applications
that requires those clock loads signal that are
referenced to a single existing clock. Loads of up to 30
pF are supported. One of the chief applications of this
component is where long traces are used to transport
clocks from their generating devices to their loads. The
creation of EMI and the degradation of waveform rise
and fall times is greatly reduced by running a single
reference clock trace to this device and then using it to
regenerate the clock that drives shorter traces. Using
these devices EMI is therefore minimized and board
real estate is saved.
Pin Configuration
NC
NC
VDD
CLK1
CLK2
VSS
VDD
CLK3
CLK4
VSS
REFIN
VDD
CLK5
CLK6
VSS
VDD
CLK7
CLK8
VSS
VDD
CLK9
VSS
VDD
SDATA
IMISC680
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 39
11 38
12 37
13 36
14 35
15 34
16 33
17 32
18 31
19 30
20 29
21 28
22 27
23 26
24 25
NC
NC
VDD
CLK18
CLK17
VSS
VDD
CLK16
CLK15
VSS
OE
VDD
CLK14
CLK13
VSS
VDD
CLK12
CLK11
VSS
VDD
CLK10
VSS
VSS
SCLOCK
Document#: 38-07026 Rev. *A
12/17/2002
Page 1 of 10

1 page




SC680E pdf
APPROVED PRODUCT
SC680E
SMBus System Clock Buffer
Maximum Ratings1
Voltage Relative to VSS:
Voltage Relative to VDD:
Storage Temperature:
Operating Temperature:
Maximum Power Supply:
-0.3V
0.3V
-65ºC to + 150ºC
0ºC to +70ºC
7V
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
Electrical Characteristics
Characteristic
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
IOL = 40mA
Output High Voltage
IOH = 30mA
Tri-State leakage Current
Dynamic Supply Current
Static Supply Current
Short Circuit Current
Input Rise Time
Symbol
VIL
VIH
IIL
IIH
VOL
Min
-
2.0
-66
-
Typ
-
-
-
Max
0.8
-
66
0.4
Units
Vdc
Vdc
µA
µA
Vdc
VOH 2.4
-
-
Vdc
Ioz
Idd66
Idd100
-
9
12
-
-
-
10
160
220
µA
mA
mA
Isdd - -
ISC 25 -
VIR 2.4 -
4
-
-
mA
mA
nS
Conditions
-
-
All Outputs (see buffer spec)
All Outputs Using 3.3V Power
(see buffer spec)
Input frequency = 66 Mhz - All outputs on
and at 30 pF load
Input frequency 100 Mhz - All outputs on
and at 30 pF load
All outputs disabled no input clock
1 output at a time - 30 seconds
.8 to 2.4 volts
VDD = VDD1 thru VDD9 =3.3V ±5%, , TA = 0ºC to +70ºC
1 Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Cypress Semiconductor Corporation
3901 North First St.
San Jose, CA 95134. Tel: 408-943-2600
http://www.cypress.com
Document#: 38-07026 Rev. *A
12/17/2002
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