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PDF ICS1887 Data sheet ( Hoja de datos )
| Número de pieza | ICS1887 | |
| Descripción | FDDI / Fast Ethernet PHYceiverTM | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS1887
FDDI / Fast Ethernet PHYceiverTM
General Description
Features
The ICS1887 is designed to provide high performance clock • Single IC solution to existing designs requiring
recovery and generation for 125 MHz serial data streams. The
multiple devices
ICS1887 is ideally suited for LAN transceiver applications in • Data and clock recovery for 125 MBaud FDDI or Fast
either FDDI or Fast Ethernet environments. The ICS1887
Ethernet applications
converts NRZ to/from NRZI data in addition to providing a • Clock multiplication from either a crystal, differential
5-bit parallel digital data transmit and receive interface.
or single-ended timing source
Clock and data recovery is performed on an input serial data • Continuous clock in the absence of data
stream or the buffered transmit data depending upon the state • No external PLL components
of the loopback input. A continuous clock source will • Lock/Loss status indicator output
continue to be present even in the absence of input data. • Loopback mode for system diagnostics
All internal timing is derived from either a low cost crystal,
differential or single-ended source.
•
Selectable loop timing mode
• PECL driver with settable sink current
The ICS1887 utilizes advanced CMOS phase-locked loop • Parallel digital transmit and receive data interface
technology which combines high performance and low power • NRZ to/from NRZI data conversion
at a greatly reduced cost.
• Consult ICS for optional configurations and data rates
Block Diagram
Pin Configuration
ICS1887RevF112596
28-Pin SOIC
PHYceiver is a trademark of Integrated Circuit Systems, Inc.
1 page  
ICS1887
Substituting the ICS1887
for the AMD PDR & PDT
This note describes the issues involved in re-
placing the AMD PDR & PDT with the
ICS1887.
There are a number of implementation differ-
ences between AMD’s PDR & PDT and the
ICS1887. This note describes the differences
and how they affect an application.
Signal Detect
Many twisted pair and fiber optic transceivers
provide a signal detect indication that becomes
active when the amount of energy being re-
ceived reaches a threshold that makes it appear
to be data and not ambient noise.
The AMD PDR device has a single ended
PECL input (SDI) and provides a TTL level
output (SDO) that tracks the input. The input
controls the source that the PLL locks to. When
signal detect is asserted, the PLL locks to the
incoming receive data. When signal detect is
deasserted, the PLL locks to the LSCLK input
to prevent locking to an off center frequency.
The current ICS1887 device provides a single
TTL-compatible input, carrier detect (CD~).
When carrier detect is asserted, the ICS1887
locks to the incoming receive data. When car-
rier detect is deasserted, or if carrier detect is
asserted and no data is present on the receive
inputs, the PLL will free run and continue to
provide RXCLK at the nominal 25 MHz
frequency. This allows the carrier detect input
to always be tied to an asserted level (ground).
If a true signal detect is required by a chip that
connects to the ICS1887, a simple, low cost
PECL to CMOS converter can be used. The
following circuit implements this function:
CD PECL Input: Board Layout Options
Option 1
Differential PECL to CMOS Conversion Circuit
Option 2
Single-Ended PECL to CMOS Conversion Circuit
5
5 Page 
5-Bit Interface – Synchronous Transmit Timing
ICS1887
T# PARAMETER (conditions)
t1 TD[4:0] Setup to TCLK rise
t2 TD[4:0] Hold after TCLK rise
MIN
10
0
TYP
MAX
UNITS
— — ns
— — ns
5-Bit Interface – Synchronous Receive Timing
T# PARAMETER (conditions)
t1 RD[4:0] Setup to RCLK rise
t2 RD[4:0] Hold after RCLK rise
MIN
13.0
12.5
TYP
MAX
UNITS
— — ns
— — ns
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ICS1887.PDF ] | |
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