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PDF ICS1522 Data sheet ( Hoja de datos )
| Número de pieza | ICS1522 | |
| Descripción | User-Programmable Video Clock Generator/ Line-Locked Clock Regenerator | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
ICS1522
User-ProgrammableVideo Clock Generator/ Line-Locked
Clock Regenerator
General Description
The ICS1522 is a very high performance monolithic phase-
locked loop (PLL) frequency synthesizer. Utilizing ICS’s
advanced CMOS mixed-mode technology, the ICS1522
provides a low-cost solution for high-end video clock
generation where synchronization to an external video
source is required.
The ICS1522 has differential video clock outputs (CLK+
and CLK-) that are compatible with industry standard
video DAC.
Operating frequencies are fully programmable with direct
control provided for reference divider, feedback divider
and postscaler.
Features
• Serial programming: Feedback and reference divisors,
VCO gain, phase comparator gain, relative phase and
test modes.
• Supports high-resolution graphics - Differential CLK
out-puts to 230 MHz
• Eliminates need for multiple ECL output voltage control-
led crystal oscillators and external components
• Fully-programmable synthesizer capability - not just a
clock multiplier
• Line-locked clock generation capability;
15 - 100 kHz
• External feedback loop capability allows graphics
system to be used as the feedback divisor with
synchronous switchover to internal feedback
• Small footprint 24-pin SOIC
• Coarse and fine phase adjustment permits precise
clocking in video recovery application
Block Diagram
Applications
• LCD Projector Systems
• Multimedia video line locking
• Genlock applications
1522RevF050697P
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.
1 page  
ICS1522
ICS1522 Register Definition
REG#
0
BIT(S)
0-10
BIT REF.
F[0:10]
1 0-7 LO[0:7]
2 0-7 HI[0:7]
3 0-9 R[0:9]
3 10 REF_POL
4 0-2 VCO[0:2]
DESCRIPTION
Feedback Divider (Default=04F, Modulus=80) Divides the VCO
by the set modulus Modulus Range=64 to 2048;
Modulus=Value+1
Feedback Sync Pulse LO (Default=03) Feedback Divider output,
but with programmable phase; LO[0:7] <F[3:10].
Feedback Sync Pulse HI (Default=06) Feedback Divider output,
but with programmable phase; HI[0:7] <F[3:10].
Reference Divider (Default=013, Modulus=20) Divides the
XTAL/EXTREF by the set modulus Modulus Range=1 to 1024;
Modulus=Value+1
External Reference Polarity (Default=0) 0=Positive Edge;
1=Negative Edge
VCO Gain (Default=4)
VCO(2)
0
0
0
0
1
1
1
1
VCO(1)
0
0
1
1
0
0
1
1
VCO(0)
0
1
0
1
0
1
0
1
VCO GAIN
10 MHz/V
15 MHz/V
20 MHz/V
25 MHz/V
45 MHz/V
60 MHz/V
75 MHz/V
90 MHz/V
5
5 Page 
ICS1522
AC Characteristics
SYMBOL
Fvco
Fxtal
Cpar
FHSYNC
Txhi
Txlo
TJIT
Tlock
Idd
Iddo
TFINE
VFINE
A
A
A
A
A
A
A
A
A
TSKEW
FCLK
VCO
PFD
PARAMETER
MIN
VCO Frequency
14
Crystal Frequency
5
Crystal Oscillator Loading Capacitance
Horizontal Sync Rate
15
XTAL1 High Time (when driven externally)
8
XTAL1 Low Time (when driven externally)
8
Phase Jitter (see Note 1)
PLL Acquire Time (to within 1%)
VDD Supply Current
VDDO Supply Current
(excluding CLK+/- termination)
ANALOG INPUTS
Fine Phase Adjustment Range
0
Control Voltage for FINE
0
FINE Input Bias Current
Capacitance of FINE Input
Bandwidth of FINE Input (3dB)
0.5
DIGITAL INPUT
SELn, SDATA Setup Time
10
SELn, SDATA Hold Time
10
SCLK Pulse Width (Thi or Tlo)
20
SCLK Frequency
Phase-frequency detector enable time
Phase-frequency detector disable time
DIGITAL OUTPUTS
Time Skew between CLK+, CLK-
CLK+ and CLK- Clock Rate
GAINS
VCO Gain, VCO(0:2)
10
Phase Detector Gain, PFD (0:2)
.23
TYP
20
15
20
MAX
230
20
100
1
500
UNITS
MHz
MHz
pF
kHz
ns
ns
ns
ms
mA
mA
15
VDD/2
20
100
1.5
ns
VDC
nA
pf
kHz
ns
ns
ns
20 MHz
50 ns
50 ns
500 ps
230 MHz
90 MHz/V
120 mA/2prad
Note 1: TJIT is the total uncertainty of the phase measured at the start of a video line on a 350 MHz oscilloscope under
these conditions: HSYNC pin driven with crystal oscillator at 48.363 kHz; FVCO = 65.000 MHz; M =0 (divide
by 1 on the output; and N = 1343 (1344 clocks per line).
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ICS1522.PDF ] | |
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