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PDF HD6417615 Data sheet ( Hoja de datos )
| Número de pieza | HD6417615 | |
| Descripción | Hardware Manual | |
| Fabricantes | Hitachi Semiconductor | |
| Logotipo |  |
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To all our customers
Regarding the change of names mentioned in the document, such as
Hitachi Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were
transferred to Renesas Technology Corporation on April 1st 2003.
These operations include microcomputer, logic, analog and discrete devices,
and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors,
and other Hitachi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp.
Thank you for your understanding. Except for our corporate trademark,
logo and corporate statement, no changes whatsoever have been made to the
contents of the document, and these changes do not constitute any alteration
to the contents of the document itself.
Renesas Technology Home Page: www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
Renesas Technology Corp.
1 page  
Contents
Section 1 Overview............................................................................................................
1.1 Features of SuperH Microcomputer with On-Chip Ethernet Controller............................
1.2 Block Diagram ...................................................................................................................
1.3 Pin Description...................................................................................................................
1.3.1 Pin Arrangement ...................................................................................................
1.3.2 Pin Functions ........................................................................................................
1.3.3 Pin Multiplexing ...................................................................................................
1.4 Processing States................................................................................................................
1
1
13
14
14
15
21
27
Section 2 CPU .....................................................................................................................
2.1 Register Configuration.......................................................................................................
2.1.1 General Registers..................................................................................................
2.1.2 Control Registers ..................................................................................................
2.1.3 System Registers...................................................................................................
2.1.4 DSP Registers .......................................................................................................
2.1.5 Notes on Guard Bits and Overflow Treatment .....................................................
2.1.6 Initial Values of Registers ....................................................................................
2.2 Data Formats......................................................................................................................
2.2.1 Data Format in Registers ......................................................................................
2.2.2 Data Formats in Memory......................................................................................
2.2.3 Immediate Data Format ........................................................................................
2.2.4 DSP Type Data Formats .......................................................................................
2.2.5 DSP Type Instructions and Data Formats ............................................................
2.3 CPU Core Instruction Features ..........................................................................................
2.4 Instruction Formats ............................................................................................................
2.4.1 CPU Instruction Addressing Modes .....................................................................
2.4.2 DSP Data Addressing ...........................................................................................
2.4.3 Instruction Formats for CPU Instructions.............................................................
2.4.4 Instruction Formats for DSP Instructions .............................................................
2.5 Instruction Set ....................................................................................................................
2.5.1 CPU Instruction Set ..............................................................................................
2.5.2 DSP Data Transfer Instruction Set........................................................................
2.5.3 DSP Operation Instruction Set..............................................................................
2.5.4 Various Operation Instructions .............................................................................
31
31
31
33
36
37
40
40
41
41
41
42
42
44
48
52
52
56
62
66
72
73
89
93
96
Section 3 Oscillator Circuits and Operating Modes ................................................ 105
3.1 Overview............................................................................................................................ 105
3.2 On-Chip Clock Pulse Generator and Operating Modes..................................................... 105
3.2.1 Clock Pulse Generator .......................................................................................... 105
i
5 Page 
Section 9 Ethernet Controller (EtherC) ....................................................................... 371
9.1 Overview............................................................................................................................ 371
9.1.1 Features ................................................................................................................. 371
9.1.2 Configuration........................................................................................................ 372
9.1.3 Pin Configuration.................................................................................................. 374
9.1.4 Ethernet Controller Register Configuration.......................................................... 375
9.2 Register Descriptions ......................................................................................................... 376
9.2.1 EtherC Mode Register (ECMR)............................................................................ 376
9.2.2 Receive Frame Length Register (RFLR).............................................................. 379
9.2.3 EtherC Status Register (ECSR) ............................................................................ 380
9.2.4 EtherC Status Interrupt Permission Register (ECSIPR) ....................................... 381
9.2.5 PHY Interface Register (PIR) ............................................................................... 382
9.2.6 PHY Interface Status Register (PSR) ................................................................... 383
9.2.7 MAC Address High Register (MAHR) ................................................................ 384
9.2.8 MAC Address Low Register (MALR) ................................................................. 385
9.2.9 Tx Retry Over Counter Register (TROCR).......................................................... 386
9.2.10 Collision Detect Counter Register (CDCR).......................................................... 387
9.2.11 Lost Carrier Counter Register (LCCR)................................................................. 388
9.2.12 Carrier Not Detect Counter Register (CNDCR) ................................................... 389
9.2.13 Illegal Frame Length Counter Register (IFLCR).................................................. 390
9.2.14 CRC Error Frame Counter Register (CEFCR) ..................................................... 391
9.2.15 Frame Receive Error Counter Register (FRECR ) ............................................... 392
9.2.16 Too-Short Frame Receive Counter Register (TSFRCR) ...................................... 393
9.2.17 Too-Long Frame Receive Counter Register (TLFRCR ) ..................................... 394
9.2.18 Residual-Bit Frame Counter Register (RFCR) ..................................................... 395
9.2.19 Multicast Address Frame Counter Register (MAFCR) ........................................ 396
9.3 Operation............................................................................................................................ 397
9.3.1 Transmission ......................................................................................................... 397
9.3.2 Reception .............................................................................................................. 399
9.3.3 MII Frame Timing ................................................................................................ 401
9.3.4 Accessing MII Registers ....................................................................................... 403
9.3.5 Magic Packet™ Detection .................................................................................... 406
9.3.6 CPU Operating Mode and Ethernet Controller Operation.................................... 407
9.4 Connection to PHY-LSI..................................................................................................... 408
Section 10 Ethernet Controller Direct Memory Access Controller
(E-DMAC) ........................................................................................................ 411
10.1 Overview............................................................................................................................ 411
10.1.1 Features ................................................................................................................. 411
10.1.2 Configuration........................................................................................................ 412
10.1.3 Descriptor Management System ........................................................................... 413
10.1.4 Register Configuration.......................................................................................... 413
10.2 Register Descriptions ......................................................................................................... 415
vii
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| PDF Descargar | [ Datasheet HD6417615.PDF ] | |
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