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PDF NE8023A Data sheet ( Hoja de datos )
| Número de pieza | NE8023A | |
| Descripción | MCC Manchester Code Converter Manual | |
| Fabricantes | LSI Logic Corporation | |
| Logotipo |  |
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80820233AA
MCCTM Manchester
Code Converter
92123
Features
s Compatible with IEEE 802.3 /Ethernet (10BASE5),
IEEE802.3/CHEAPERNET (10BASE2) and Ethernet
Rev. 1 Specifications
s Compatible with 8003 ELDC ®, 8005 Advanced
EDLC and Intel 82586 LAN Controller
s Manchester Data Encoding/Decoding and
Receiver Clock Recovery with Phase Locked
Loop (PLL)
s Receiver and Collision Squelch Circuit and Noise
Rejection Filter
s Differential TRANSMIT Cable Driver
s Loopback Capability for Diagnostics and
Isolation
s Fail-Safe Watchdog Timer Circuit to Prevent
Continuous Transmission
s 20 MHz Crystal Oscillator
s Transceiver Interface High Voltage (16 V) Short
Circuit Protection
s Low Power CMOS Technology with Single 5V
Supply
s 20 pin DIP (Commercial) &
20 pin PLCC Packages (Commercial, Extended)
s Temperature Ranges,
• Commercial 0°C to +70°C
• Extended –40°C to +85 °C
Functional Block Diagram
TxEN
WATCHDOG
TIMER
TxC
ENCODER
TxD
Tx+
Tx–
LPBK/
WDTD
TRANSMIT
VCC
CSN
CARRIER
SENSE
VSS
MODE 1
X1
X2
mRxC
oRxD
XTAL
CLOCK
DECODER
MUX
RECEIVE
MODE 2
Rx+
Rx–
u.cCOLL
10MHz
DETECTOR
COLL+
COLL–
COLLISION
t4Figure 1. 8023A MCC Manchester Code Converter
e Block Diagram.
heMCC is a trademark of SEEQ Technology, Inc.
sEDLC is a registered trademark of SEEQ Technology, Inc.
www.dataMD400022/D
1
Note: Check for latest Data Sheet revision
before starting any designs.
SEEQ Data Sheets are now on the Web, at
www.lsilogic.com.
This document is an LSI Logic document. Any
reference to SEEQ Technology should be
considered LSI Logic.
Description
The SEEQ 8023A Manchester Code Converter chip pro-
vides the Manchester data encoding and decoding func-
tions of the Ethernet Local Area Network physical layer. It
interfaces to the SEEQ 8003 and 8005 Ethernet Data Link
Controllers or to the Intel 82586 LAN Controller and any
standard Ethernet transceiver as defined by IEEE 802.3
and Ethernet Revision 1.
Pin Configuration
DUAL-IN-LINE
TOP VIEW
(Commercial Temp Only)
MODE 1
MODE 2
LPBK/WDTD
Rx+
Rx–
(CSN) CSN
(COLL) COLL
(RxC) RxC
RxD
VSS
1 20
2 19
3 18
4 17
5 16
8023A
6 15
7 14
8 13
9 12
10 11
V CC
Tx+
Tx–
TxD
TxC
TxEN (TxEN)
X1
X2
COLL+
COLL–
PLASTIC LEADED CHIP CARRIER
TOP VIEW
(Commercial and Extended Temps)
3 2 1 20 19
Rx+ 4
Rx– 5
(CSN) CSN 6
(COLL) COLL 7
(RxC) RxC 8
18 Tx–
17 TxD
16 TxC
15 TxEN (TxEN)
14 X1
9 10 11 12 13
1 page  
8023A
MODE signal active HIGH, or by allowing it to float HIGH
with its internal pullup. In this configuration, RxC, TxEN,
CSN and COLL become active LOW. In addition, RxD is
HIGH during idle, and RxC has 1.2 µs discontinuity during
signal acquisition.
LPBK/WDTD Loopback/Watchdog Timer Disable
(Input):
Normal Operation: For normal operation this pin should
be HIGH or tied to VCC. In normal operation the watchdog
timer is enabled.
Loopback: When this pin is brought low, the Manchester
encoded transmit data from TxD and TxC is routed through
the receiver circuit and sent back onto the RxD and RxC
Pins. During loopback, Collision and Receive data inputs
are ignored. The transmit pair is idled. At the end of
transmission, the signal quality error test (SQET) will be
simulated by asserting collision during the inhibit window.
During loopback, the watchdog timer is enabled.
Watchdog Timer Disable: When this pin is between 10 V
(Min.) and 16 V (Max.), the on chip 25 ms Watchdog Timer
will be disabled. The watchdog timer is used to monitor the
transmit enable pin. If TxEN is asserted for longer than
25 ms, then the watchdog timer (if enabled) will automati-
cally deassert CSN and inhibit any further transmissions
on the Tx+ and Tx- lines. The watchdog timer is automati-
cally reset each time TxEN is deasserted.
Interconnection to a Data Link Controller
Figure 5 shows the interconnections between the 8023A
MCC and SEEQ’s 8003 or 8005. There are three connec-
tions for each of the two transmission channels, transmit
and receive, plus the Collision Signal line (COLL).
Transmitter connections are:
Transmit Data, TxD
Transmit Clock, TxC
Transmit Enable, TxEN
Collision, COLL
Receiver connections are:
Receive Data, RxD
Receive Clock, RxC
Carrier Sense, CSN
Compatibility with Other LAN Controllers
SEEQ’s 8023A is compatible with other LAN Controllers,
such as the 82586, when Pin 2 (MODE2) of the 8023A is
floating or tied to VCC. In this mode of operation, timing and
polarity on the controller interface lines are compatible,
with the 82586 specifications dated March 1984.
Use of Time Domain Reflectometry in the 82586 is not
recommended since the TDR transmission does not have
a valid preamble.
D.C. and A.C. Characteristics and
Timing
Crystal Specification
Resonant Frequency (CL = 20 pF) ..................... 20 MHz
± 0.005% 0-70° C
and ± 0.003% at 25° C
Type ................................................. Fundamental Mode
Circuit .............................................. Parallel Resonance
Load Capacitance (CL) ........................................... 20pF
Shunt Capacitance (CO) .................................. 7pF Max.
Equivalent Series Resistance (R1) ................. 25Ω Max.
Motional Capacitance (C1) ........................ 0.02 pF Max.
Drive Level ............................................................. 2mW
TxD
TxC
TxEN
LOOPBACK [1]
8003
OR
8005
COLL
RxD
RxC
CSN
TxD
TxC
TxEN
LOOPBACK
8023A
MCC
COLL
RxD
RxC
CSN
MODE 2
Figure 5. Interconnection of 8023A and 8003/8005
NOTE
1. Loopback output on 8005 only.
MD400022/D
5
R1 C1 L1
C0
EQUIVALENT CIRCUIT OF CRYSTAL
Figure 6.
5 Page 
8023A
Rx(+)
Rx(–)
MODE 2 = 0
CSN
(–)
(+)
t 21
RxC
t 23A
t 23B
RxD
MODE 2 = 1
CSN
t 21
t31 t 31
t 26
RxC FOLLOWS TxC
(–) (+)
(+) (–)
t 27 t 26
t 28
t 25A
t 28
t 25B
RxC
RxD
t 32
t 33
t 25A
t 25B
t 36
Figure 9. Receive Timing-Start of Packet
MODE 2 = 0
RxC
Rx(+)
Rx(–)
(LAST BIT = 0)
t29
(–)
(+)
CSN
RxD
t27
(+)
(–)
t 23A
t 29
t 23B
t 22
"1" "0"
t 30
t35
MODE 2 = 1
RxC
Rx(+)
Rx(–)
(LAST BIT = 1)
CSN
RxD
t 29
t 34
(–) (+)
(+) (–)
t 24
"1" | "1" |
t 27
t 30
Figure 10. Receive Timing — End of Packet
MD400022/D
11
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| PDF Descargar | [ Datasheet NE8023A.PDF ] | |
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