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PDF GM71VS17800CL Data sheet ( Hoja de datos )
| Número de pieza | GM71VS17800CL | |
| Descripción | (GM71VS17800CL / GM71V17800C) 2M x 8-Bit CMOS DRAM | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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Description
The GM71V(S)17800C/CL is the new
generation dynamic RAM organized 2,097,152
x 8 bit. GM71V(S)17800C/CL has realized
higher density, higher performance and various
functions by utilizing advanced CMOS process
technology. The GM71V(S)17800C/CL offers
Fast Page Mode as a high speed access mode.
Multiplexed address inputs permit the
GM71V(S)17800C/CL to be packaged in
standard 400 mil 28pin plastic SOJ, and
standard 400mil 28pin plastic TSOP II. The
package size provides high system bit densities
and is compatible with widely available
automated testing and insertion equipment.
Pin Configuration
GM71V17800C
GM71VS17800CL
2,097,152 WORDS x 8 BIT
CMOS DYNAMIC RAM
Features
* 2,097,152 Words x 8 Bit Organization
* Fast Page Mode Capability
* Single Power Supply (3.3V+/-0.3V)
* Fast Access Time & Cycle Time
(Unit: ns)
t tRAC CAC tRC tPC
GM71V(S)17800C/CL-5
GM71V(S)17800C/CL-6
GM71V(S)17800C/CL-7
50 13 90 35
60 15 110 40
70 18 130 45
* Low Power
Active : 468/432/396mW (MAX)
Standby : 7.2mW (CMOS level : MAX)
0.54mW (L- version : MAX)
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
* All inputs and outputs TTL Compatible
* 2048 Refresh Cycles/32ms
* 2048 Refresh Cycles/128ms (L-version)
* Self Refresh Operation (L-version)
* Battery Back Up Operation (L- version)
28 SOJ
VCC 1
I/O0 2
I/O1 3
I/O2 4
I/O3 5
WE 6
RAS 7
NC 8
A10 9
A0 10
A1 11
A2 12
A3 13
mVCC 14
www.datasheet4u.coRev 0.1 / Apr’01
28 VSS
27 I/O7
26 I/O6
25 I/O5
24 I/O4
23 CAS
22 OE
21 A9
20 A8
19 A7
18 A6
17 A5
16 A4
15 VSS
28 TSOP II
VCC 1
I/O0 2
I/O1 3
I/O2 4
I/O3 5
WE 6
RAS 7
NC 8
A10 9
A0 10
A1 11
A2 12
A3 13
VCC 14
28 VSS
27 I/O7
26 I/O6
25 I/O5
24 I/O4
23 CAS
22 OE
21 A9
20 A8
19 A7
18 A6
17 A5
16 A4
15 VSS
(Top View)
1 page  
Read Cycle
Symbol
Parameter
tRAC Access Time from RAS
tCAC Access Time from CAS
tAA Access Time from Address
tOAC Access Time from OE
tRCS Read Command Setup Time
tRCH Read Command Hold Time to CAS
tRRH Read Command Hold Time to RAS
tRAL Column Address to RAS Lead Time
tCAL Column Address to CAS Lead Time
tCLZ CAS to Output in Low-Z
tOH Output Data Hold Time
tOHO Output Data Hold Time from OE
tOFF Output Buffer Turn-off Time
tOEZ Output Buffer Turn-off Time to OE
tCDD CAS to DIN Delay Time
GM71V17800C
GM71VS17800CL
GM71V(S)17800 GM71V(S)17800 GM71V(S)17800
C/CL-5
C/CL-6
C/CL-7
Min Max Min Max Min Max
Unit
Note
- 50 - 60 - 70 ns 8,9
- 13 - 15 - 18
ns 9,10,17
- 25 - 30 - 35
ns 9,11,17
- 13 - 15 - 18 ns
9
0- 0- 0-
ns
0 - 0 - 0 - ns 12
5 - 5 - 5 - ns 12
25 - 30 - 35 -
ns
25 - 30 - 35 -
ns
0- 0- 0-
ns
3- 3- 3-
ns
3- 3- 3-
ns
- 13 - 15 - 15 ns 13
- 13 - 15 - 15 ns 13
13 - 15 - 18 - ns 5
Write Cycle
Symbol
Parameter
tWCS
tWCH
tWP
tRWL
tCWL
tDS
tD
H
Write Command Setup Time
Write Command Hold Time
Write Command Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data-in Setup Time
Data-in Hold Time
GM71V(S)17800 GM71V(S)17800 GM71V(S)17800
C/CL-5
C/CL-6
C/CL-7
Min Max Min Max Min Max
0 - 0- 0-
8 - 10 - 15 -
8 - 10 - 10 -
13 - 15 - 18 -
13 - 15 - 18 -
0 - 0- 0-
8 - 10 - 15 -
Unit
ns
ns
ns
ns
ns
ns
ns
Note
14
15
15
Rev 0.1 / Apr’01
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet GM71VS17800CL.PDF ] | |
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