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GS832036 Datasheet دیتاشیت PDF دانلود

دیتاشیت - ETC - (GS832018/32/36) Sync Burst SRAMs

شماره قطعه GS832036
شرح مفصل (GS832018/32/36) Sync Burst SRAMs
تولید کننده ETC 
آرم ETC 


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GS832036 شرح
Preliminary
GS832018/32/36T-250/225/200/166/150/133
100-Pin TQFP
Commercial Temp
Industrial Temp
2M x 18, 1M x 32, 1M x 36
36Mb Sync Burst SRAMs
250 MHz133 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
Features
• FT pin for user-configurable flow through or pipeline
operation
• Single Cycle Deselect (SCD) operation
• 2.5 V or 3.3 V +10%/10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
• Pb-Free 100-lead TQFP package available
Functional Description
Applications
The GS832018/32/36T is a 37,748,736-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS832018/32/36T operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (VDDQ) pins are used to decouple output noise
from the internal circuits and are 3.3 V and 2.5 V compatible.
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
Pipeline
tKQ
tCycle
2.5 2.7 3.0 3.5 3.8 4.0 ns
4.0 4.4 5.0 6.0 6.6 7.5 ns
3-1-1-1 Curr (x18) 285 265 245 220 210 185 mA
Curr (x32/x36) 350 320 295 260 240 215 mA
Flow
Through
2-1-1-1
tKQ
tCycle
Curr (x18)
Curr (x32/x36)
6.5
6.5
205
235
7.0
7.0
195
225
7.5
7.5
185
210
8.0
8.0
175
200
8.5
8.5
165
190
8.5
8.5
155
175
ns
ns
mA
mA
Rev: 1.02 10/2004
1/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology

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