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PDF CE2746 Data sheet ( Hoja de datos )
| Número de pieza | CE2746 | |
| Descripción | 6-Channel Audio DAC 24-bit 192kHz | |
| Fabricantes | ETC | |
| Logotipo |  |
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Microelectronics
CE2746
6-Channel Audio DAC, 24-bit, 192kHz
DESCRIPTION
The CE2746 is a mixed signal CMOS monolithic audio
digital to analog converter. It contains six 1-bit sigma delta
DAC. The system consists of 128-time interpolation filters,
4th order Σ∆ modulators, switch capacitors and analog
reconstruction filters. The one bit Σ∆ converter offers
superior differential linearity, with no distortion due to
component mis-match. high tolerance to clock jitter.
The CE2746 support data conversion from 32K to
192KHz. The analog section operates at 5 volt while the
digital section at 3.3 volt. This dual voltage system reduces
not only the power consumption but also the noise caused
by the digital circuit switching. The CE2746 is ideal for
DVD player, AV receiver and set-top box application.
The CE2746 support 24, 20, 18 and 16-bit input data. It
also support multiple sampling frequency data. Each DAC
has its own individual volume control.
FEATURES
• Six Channel Audio DAC.
- 104 dB SNR (A Weighted).
- -94 dB THD + N Ratio (A Weighted).
- 8K - 192 KHz. Sampling Rates.
- Independent Digital Volume Control.
- I2S, Left and Right Justified Digital Input Formats.
- On -chip Reconstruction Filters.
• 3.3 -volt Digital Interface.
• 2-wire Serial Control Interface.
• 3.3 Volt Digital. 5 Volt Analog Power Supply.
Applications
• Digital Surround Sound For Home Theatre
• DVD
• Car Audio.
XCK PLL
DIN1
DIN2
DIN3
80
80
77
LRCK
BCK
77
78
DIGITAL
AUDIO
INPUT
Format
Detect'n
CEI Microelectronics Co. Ltd.
CE2746
INTERPOLATION
FILTER
Σ∆
Mod.
Σ∆
Mod.
Σ∆
Mod.
D/A
D/A
D/A
D/A
D/A
D/A
Control Interface
SDA
SCL
15
RST
15
VCM
AR1
AL1
AR2
AL2
AR3
AL3
1-18 March 24, 2004
1 page  
CE2746
PIN DESCRIPTION (Continued)
Pin Name
DGND
TSTOUT
SDA
Pin #
11
12
13
Type
GND
T
I/O
Description
Digital ground
Tri-state output pin, This pin can be connected to ground or leave open
I2C data bus. Open drain output. Externally this pin should tie to a 680 ohm pull up
resistor.
SCL
Analog
AVDD
AR1
GR0
AL1
AGND
AR2
GR1
AL2
AGND
AR3
GR2
AL3
VCM
AVDD
14 I I2C clock input.
28 +5V Analog circuits power supply.Should be Connected to a 22 uF capacitor in parallel with
a 0.1 uF.
27 O Analog right channel 1 output
26 GND Analog circuits ground
25 O Analog left channel 1 output
24 GND Analog circuits ground
23 O Analog right channel 2 output
22 GND Analog circuits ground
21 O Analog left channel 2 output
20 GND Analog circuits ground
19 O Analog right channel 3 output
18 GND Analog circuits ground
17 O Analog right channel 3 output
16 I/O Common voltage De-coupling Pin Should be Connected to a 22 uF capacitor in parallel
with a 0.1 uF.
15 +5V Analog circuits power supply.Should be Connected to a 22 uF capacitor in parallel with
a 0.1 uF.
5-18 March 24, 2004
5 Page 
CE2746
AUTODET Automatically detects the serial audio input data sampling rate
0: - do not use auto-detect
1: - automatically detects the serial audio input data sampling rate.
FS384: 384 fs or 256 fs control for the PLL clock output
0: the PLL takes the reference clock and multiplies it by 2 to generate a 512 bit clock
1: the PLL takes the reference clock and multiplies it by 4/3 to generate a 512 bit clock
CKDIV4: Clock divider enable control
0: do not enable input clock divided by 4
1: enable input clock divided by 4
CKDIV2: Clock divider enable control
0: do not enable input clock divided by 2
1: enable input clock divided by 2
MUTE56: Mute control for channels 5 and 6
0: do not mute channels 5 and 6
1: simultaneously mute channels 5 and 6
MUTE34: Mute control for channels 3 and 4
0: do not mute channels 3 and 4
1: simultaneously mute channels 3 and 4
MUTE12: Mute control for channels 1 and 2
0: do not mute channels 1 and 2
1: simultaneously mute channels1 and2
Volume Registers for channel 1 to channel 3, (ADRS=hex02 - hex07, default=hex80)
ADDR[3:0]
Hex 02
Hex 03
Hex 04
Hex 05
Hex 06
Hex 07
Default Value
Volume Registers
BIT 7
BIT 6
BIT 5
BIT 4
Channel 1 left volume register, VOLREGL1[7:0]
Channel 1 right volume register, VOLREGR1[7:0]
Channel 2 left volume register, VOLREGL2[7:0]
Channel 2 right volume register, VOLREGR2[7:0]
Channel 3 left volume register, VOLREGL3[7:0]
Channel 3 right volume register, VOLREGR3[7:0]
1000
BIT 3
0
BIT 2
0
BIT 1
0
VOLREG:- Control the volume of the 6 DAC’s
80h- corresponds to 0 dB setting. Value should not be programed greater than 80h.
BIT 0
0
11-18
March 24, 2004
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet CE2746.PDF ] | |
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