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PDF TC90A66F Data sheet ( Hoja de datos )
| Número de pieza | TC90A66F | |
| Descripción | TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic | |
| Fabricantes | Toshiba Semiconductor | |
| Logotipo |  |
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Preliminary TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC90A66F
PAP/PIP/POP Controller for Wide-Screen TVs (PAL/NTSC)
TC90A66F
With built-in AD and DA converters (ADC/DAC), the TC90A66F is a picture-and-picture (PAP)/picture-in-picture
(PIP)/picture-out-picture (POP) controller IC for PAL and NTSC
formats. It is used in combination with field memory, video signal
processor ICs.
The TC90A66F enables a variety of picture display functions.
The IC is optimal to provide wide-screen TVs with additional
functionality.
Features
• Two-channel 8-bit ADC, three-channel 8-bit DAC, clamp
circuit, and multiplexer integrated on single chip
Weight: 4.64 g (typ.)
• External field memory
Recommended memory: MSM51V8221, MSM51V8222 (By Oki)
• Picture display functions
PAP display
Half-picture left and right sides of 16:9 screen
(Motion Picture mode or Still mode selectable)
PIP display
4:3 or 16:9 aspect ratio
(Motion Picture mode or Still mode selectable)
POP display
4:3 aspect ratio
(3 pictures in Still mode, 1 picture in Motion Picture mode and 2 pictures in Still mode, or
Strobe mode selectable)
Multi-picture still Display of up to 24 still pictures per screen
Channel search
9, 12, or 16 picture search
(Still mode, Strobe mode, or 1 picture in Motion Picture mode selectable)
• Variable frame width and frame color
• Built-in horizontal and vertical filters
• I2C bus for micro controller interface
• 3.3-V single power supply
• Package: QFP144
www.datasheet4u.com
1
2001-06-07
1 page  
Pin Functions (144-pin QFP)
Pin
Number Pin Name I/O
Function
1 ADVDD Power supply for A/D (3.3 V)
2 YINS
I A/D Y signal (S system) input
3 ADVSS
4 IINS
GND for A/D
I A/D I signal or R-Y signal (S system) input
5 ADVDD Power supply for A/D (3.3 V)
6 QINS
I A/D Q signal or B-Y signal (S system) input
7 ADVSS
8 VRTY
GND for A/D
I Reference voltage for A/D Y signal (top)
9 VRBY
I Reference voltage for A/D Y signal (bottom)
10 VRTC
I Reference voltage for A/D I, Q signal (top)
11 VRBC
I Reference voltage for A/D I, Q signal (bottom)
12 ADVDD
13 YINE
Power supply for A/D (3.3 V)
I A/D Y signal (E system) input
14 ADVSS
15 IINE
GND for A/D
I A/D I signal or R-Y signal (E system) input
16 AVDD
17 QINE
Power supply for analog circuit (3.3 V)
I A/D Q signal or B-Y signal (E system) input
18 AVSS
19 VDD
20 CNT2
GND for analog circuit
Power supply (3.3 V)
O Test output pin
21 CNT1
O Test output pin
22 CNT0
O Test output pin
23 CLAMP O Clamp signal monitor output
24 TIN9
I Test input pin (connect to GND)
25 TIN8
I Test input pin (connect to GND)
26 TIN7
I Test input pin (connect to GND)
27 TIN6
I Test input pin (connect to GND)
28 TIN5
I Test input pin (connect to GND)
29 TIN4
I Test input pin (connect to GND)
30 TIN3
I Test input pin (connect to GND)
31 TIN2
I Test input pin (connect to GND)
32 TIN1
I Test input pin (connect to GND)
33 TIN0
34 WVDE
35 WHDE
I Test input pin (connect to GND)
I (E system) vertical sync signal input (It can be inverted using I2C bus)
I (E system) horizontal sync signal input (It can be inverted using I2C bus)
36 VSS
37 WCKE
GND
I (E system) system clock input
38 WHREFE I/O (E system) PLL phase comparison output
39 VDD
40 HRST
Power supply (3.3 V)
O Unit adjusting pin
41 MOH
O Memory use switch signal [(YCS (L)㨯TC90A66F (H))
Note1: Supports 5 V interface.
5
TC90A66F
(Note1)
(Note1)
(Note1)
2001-06-07
5 Page 
TC90A66F
Pin Number Pin Name
Function
99
100
102
103
104
105
106
107
110
111
112
114
115
136
138
140
141 to 142
143
144
RHREF PLL phase compare output pin for main picture.
The HREF signal obtained by the I/N divider circuit or the phase comparison result of RHD signal. This
signal is used to control the external VCO voltage.
RCK Read clock input pin. It is composing 5 V interface.
Inputs from the external PLL circuit.
Inputs 2400 fH for both 4M and 2M memory.
RHD
RVD
YS
KAYS
Horizontal sync signal input pin for main picture (read). Inputs horizontal sync signal from VCD for main
picture. It is composing 5 V interface (negative polarity input). For negative polarity input, set sub
address [28H: RHINV] to non-inversion (L).
Vertical sync signal input pin for main picture (read). Inputs vertical sync signal from VCD for main
picture. It is composing 5 V interface (negative polarity input). For negative polarity input, set sub
address [28H: RVINV] to non-inversion (L).
Main/sub picture switch timing signal output pin. Output amplitude is 3.3 Vp-p typical. When the YS
signal is High, displays sub picture.
Wallpaper YS signal output.
HYOJUN Standard/non-standard signal output pin [standard (L)/non-standard (H)]
PWRST System reset input pin. When low input, it carries out the reset.
IICNR
At least 1 V is required as reset duration.
I2C bus noise reduction circuit setting pin.
When set to on (connect to VDD), data are latched once by the internal clock, then written to register.
When set to off (connect to GND), data are written to register directly.
SADSEL Sub address of main/sub picture switching pin. [main (H)/sub (L)]
SACN
SCL
SDA
Normally, set to L (enables sub addresses 00h to 7Fh).
I2C bus acknowledge output pin.
I2C bus serial clock input pin. It is composing 5 V interface.
I2C bus serial data input/acknowledge output pin.
It is composing 5 V interface.
YOUT
IOUT
QOUT
VB2-1
Y signal output pin. Output amplitude is 0.9 Vp-p typical.
I signal output pin. Output amplitude is 0.9 Vp-p typical.
Q signal output pin. Output amplitude is 0.9 Vp-p typical.
Bias pin for DAC.
Connect a 0.1 µF bypass capacitor between the pins and GND.
VREF DAC reference voltage input pin.
Reference voltage is 2.3 V typical.
ADBIAS Bias pin for ADC.
Connect a 0.1 µF bypass capacitor between the pin and AGND.
11 2001-06-07
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