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PDF IBM25PPC405GPR Data sheet ( Hoja de datos )
| Número de pieza | IBM25PPC405GPR | |
| Descripción | Embedded Processor | |
| Fabricantes | IBM Microelectronics | |
| Logotipo |  |
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Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Features
• IBM PowerPC 405 32-bit RISC processor core
operating up to 400MHz with 16KB I- and
D-caches
• PC-133 synchronous DRAM (SDRAM) interface
- 32-bit interface for non-ECC applications
- 40-bit interface serves 32 bits of data plus 8
check bits for ECC applications
• 4KB on-chip memory (OCM)
• External peripheral bus
- Flash ROM/Boot ROM interface
- Direct support for 8-, 16-, or 32-bit SRAM
and external peripherals
- Up to eight devices
- External Mastering supported
• DMA support for external peripherals, internal
UART and memory
- Scatter-gather chaining supported
- Four channels
• PCI Revision 2.2 compliant interface (32-bit, up
to 66MHz)
- Synchronous or asynchronous PCI Bus
interface
- Internal or external PCI Bus Arbiter
• Ethernet 10/100Mbps (full-duplex) support with
media independent interface (MII)
• Programmable interrupt controller supports 13
external and 19 internal edge triggered or level-
sensitive interrupts
• Programmable timers
• Two serial ports (16550 compatible UART)
• One IIC interface
• General purpose I/O (GPIO) available
• Supports JTAG for board level testing
• Internal processor local Bus (PLB) runs at
SDRAM interface frequency
• Supports PowerPC processor boot from PCI
memory
• Unique software-accessible 64-bit chip ID
number (ECID).
Description
Designed specifically to address embedded
applications, the PowerPC 405GPr (PPC405GPr)
provides a high-performance, low-power solution
that interfaces to a wide range of peripherals by
incorporating on-chip power management features
and lower power dissipation requirements.
This chip contains a high-performance RISC
processor core, SDRAM controller, PCI bus
interface, Ethernet interface, control for external
ROM and peripherals, DMA with scatter-gather
support, serial ports, IIC interface, and general
purpose I/O.
Technology: IBM CMOS SA-27E, 0.18 µm
(0.11 µm Leff)
Package: 456-ball (35mm or 27mm) enhanced
plastic ball grid array (E-PBGA)
Power (typical): 0.72W at 266MHz
3/14/03
While the information contained herein is believed to be accurate, such information is preliminary, and should not be
relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made.
Page 1 of 58
1 page  
PowerPC 405GPr Embedded Processor Data Sheet
PPC405GPr Embedded Controller Functional Block Diagram
Preliminary
Universal
Interrupt
Controller
16KB
D-Cache
Clock
Control
Reset
Power
Mgmt
Timers
MMU
DOCM
IOCM
PPC405
Processor Core
JTAG
DCU
Trace
ICU
OCM
SRAM
OCM
Control
DCR Bus
DCRs
GPIO IIC UART UART
16KB Arb
I-Cache
On-chip Peripheral Bus (OPB)
DMA
Controller
(4-Channel)
OPB
Bridge
MAL
Ethernet
Arb Processor Local Bus (PLB)
Code
Decompression
(CodePack)
SDRAM
Controller
13-bit addr
32-bit data
External
Bus
Controller
External
Bus Master
Controller
32-bit addr
32-bit data
PCI Bridge
66 MHz max (async)
33 MHz max (sync)
MII
The PPC405GPr is designed using the IBM Microelectronics Blue LogicTM methodology in which major
functional blocks are integrated together to create an application-specific ASIC product. This approach
provides a consistent way to create complex ASICs using IBM CoreConnectTM Bus Architecture.
3/14/03
Page 5 of 58
5 Page 
PowerPC 405GPr Embedded Processor Data Sheet
Serial Interface
• One 8-pin UART and one 4-pin UART interface provided
• Selectable internal or external serial clock to allow a wide range of baud rates
• Register compatibility with NS16550 register set
• Complete status reporting capability
• Transmitter and receiver are each buffered with 16-byte FIFOs when in FIFO mode
• Fully programmable serial-interface characteristics
• Supports DMA using internal DMA engine
IIC Bus Interface
• Compliant with Philips® Semiconductors I2C Specification, dated 1995
• Operation at 100kHz or 400kHz
• 8-bit data
• 10- or 7-bit address
• Slave transmitter and receiver
• Master transmitter and receiver
• Multiple bus masters
• Supports fixed VDD IIC interface
• Two independent 4 x 1 byte data buffers
• Fifteen memory-mapped, fully programmable configuration registers
• One programmable interrupt request signal
• Provides full management of all IIC bus protocol
• Programmable error recovery
Preliminary
3/14/03
Page 11 of 58
11 Page | ||
| Páginas | Total 58 Páginas | |
| PDF Descargar | [ Datasheet IBM25PPC405GPR.PDF ] | |
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