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PDF IBM25PPC405CR Data sheet ( Hoja de datos )
| Número de pieza | IBM25PPC405CR | |
| Descripción | Embedded Controller | |
| Fabricantes | IBM Microelectronics | |
| Logotipo |  |
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PowerPC 405CR Embedded Controller Data Sheet
Features
• IBM PowerPCTM 405 32-bit RISC processor
core operating up to 266MHz
- Memory Management Unit
- 16KB instruction and 8KB data caches
- Multiply-Accumulate (MAC) function,
including fast multiply unit
- Programmable Timers
- Supports JTAG for board level testing
• PC-100 Synchronous DRAM (SDRAM)
interface operating up to 133MHz
- 32-bit interface for non-ECC applications
- 40-bit interface serves 32 bits of data plus 8
check bits for ECC applications
• External Peripheral Bus
- Flash ROM/Boot ROM interface
- Direct support for 8-, 16-, or 32-bit SRAM
and external peripherals
- Up to eight devices
- External Mastering supported
• DMA support for external peripherals, internal
UART and memory
- Scatter-gather chaining supported
- Four channels
• Programmable Interrupt Controller supports
interrupts from a variety of sources
- Supports 7 external and 10 internal
interrupts
- Edge triggered or level-sensitive
- Positive or negative active
- Non-critical or critical interrupt to processor
core
- Programmable critical interrupt priority
ordering
- Programmable critical interrupt vector for
faster vector processing
• Two serial ports (16550 compatible UART)
• One IIC (I2C) interface
• General Purpose I/O (GPIO) available
• Internal Processor Local Bus (PLB) runs at
SDRAM interface frequency
Description
The IBM PowerPC 405CRTM is a 32-bit RISC
The PPC405CR employs the IBM CoreConnectTM
embedded controller. High performance, peripheral bus architecture. This architecture, as implemented
integration, and low cost make the device ideal for
on the PPC405CR, consists of a 64-bit, 100-MHz
wired communications, network printers, and other Processor Local Bus (PLB) and a 32-bit, 50-MHz
computing applications.
On-Chip Peripheral Bus (OPB).High-performance
mThis device is an easy upgrade for systems based
oon PowerPC 403xx embedded processors, while
.cproviding a base for custom chip designs.
uThe controller is powered by a PPC405 embedded
t4core. This core tightly couples a 266-MHz CPU,
eMMU, I- and D-cache, and debug logic. Fine-tuning
eof the core reduces data transfer overhead,
hminimizes pipeline stalls, and greatly improves
sperformance.
peripherals attach to the PLB; and less
performance-critical peripherals attach to the OPB.
Technology: IBM CMOS SA12E 0.25 µm
(0.18 µm Leff)
Package: 27mm, 316-ball enhanced plastic ball grid
array (E-PBGA)
Power (estimated): Typical 0.9W, Maximum 2.0W
.data While the information contained herein is believed to be accurate, such information is preliminary, and should not be
www relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made.
1
1 page  
PowerPC 405CR Embedded Controller Data Sheet
PPC405CR Embedded Controller Functional Block Diagram
Universal
Interrupt
Controller
Clock
Control
Reset
Power
Mgmt
Timers
MMU
PPC405
Processor Core
8KB
D-Cache
JTAG
DCU
Trace
ICU
DCR Bus
DCRs
*Serial
Clock
GPIO IIC UART UART
16KB
I-Cache
Arb On-chip Peripheral Bus (OPB)
DMA
Controller
(4-Channel)
OPB
Bridge
* See Peripheral Interface
Clock Timings table
Processor Local Bus (PLB)
Code
Decompression
(CodePack)
SDRAM
Controller
133MHz max
- 13-bit addr
- 32-bit data
External
Bus
Controller
External
Bus Master
Controller
66MHz max
- 32-bit addr
- 32-bit data
The PPC405CR is designed using the IBM Microelectronics Blue LogicTM methodology in which major
functional blocks are integrated together to create an application-specific ASIC product. This approach
provides a consistent way to create complex ASICs using IBM CoreConnectTM Bus Architecture.
Note: IBM CoreConnect busses provide:
• 64-bit PLB interfaces up to 133MHz
• 32-bit OPB interfaces up to 66MHz
5
5 Page 
PowerPC 405CR Embedded Controller Data Sheet
General Purpose IO (GPIO) Controller
• Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus
master accesses.
• All GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO
capabilities acts as a GPIO or is used for another purpose. Twenty-three GPIOs are multiplexed with:
- 7 of 8 chip selects
- All seven external interrupts
- All nine instruction trace pins
• Each GPIO output is separately programmable to emulate an open drain driver (i.e., drives to zero, three-
stated if output bit is 1).
Universal Interrupt Controller (UIC)
The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between
the various sources of interrupts and the local PowerPC processor.
Features include:
• Supports 7 external and 10 internal interrupts
• Edge triggered or level-sensitive
• Positive or negative active
• Non-critical or critical interrupt to PPC405 processor core
• Programmable critical interrupt priority ordering
• Programmable critical interrupt vector for faster vector processing
JTAG
• IEEE 1149.1 Test Access Port
• IBM RISCWatch Debugger support
• JTAG Boundary Scan Description Language (BSDL)
11
11 Page | ||
| Páginas | Total 42 Páginas | |
| PDF Descargar | [ Datasheet IBM25PPC405CR.PDF ] | |
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