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PDF L64108 Data sheet ( Hoja de datos )
| Número de pieza | L64108 | |
| Descripción | Transport With Embedded Cpu And Control | |
| Fabricantes | LSI Logic Corporation | |
| Logotipo |  |
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L64108 Transport with Embedded CPU and Control
Overview
The L64108 combines a 32-bit 54 MHz RISC CPU, a programmable transport
demultiplexer, a DVB Descrambler, a DRAM controller and other peripherals
on a single chip. This versatile device interfaces to all of the other members of
the Integra™ 1100 set-top product family. This includes a serial or parallel
input from the L64724 satellite modem or the L64768 cable modem and an
output of multiplexed audio and video PES streams to the L64105 MPEG-2
A/V Decoder. The L64108 is suitable for worldwide use in DBS, CATV, or
telco set-top boxes.
Intelligence, Flexibility, Performance
The on-chip high performance CW4001 MiniRISC® 32-bit RISC MIPS CPU
subsystem provides the set-top with intelligence, flexibility and performance.
The CPU subsystem includes 8 KB of instruction cache and 4 KB of data
cache to substantially enhance performance as well as timers and counters
that are needed by real-time operating systems. The powerful 54 MHz CPU is
capable of processing all of the set-top application and control needs. These
include complete set-top system initialization and testing, security handling,
communication ports protocol processing, remote control handling, PCR
recovery and locking, audio/video synchronization, subtitles, OSD overlay,
closed caption, teletext, and electronic program guide (EPG).
www.datasheet4u.coL64m108 Block Diagram
Features and Benefits
• ISO/IEC 13818-1 (MPEG-2) compliant trans-
port demultiplexer
- 32 PIDs support
- Sustained input rate up to 60 Mbits/sec
serial and 9 Mbytes/sec parallel
- Extensive and fully programmable
hardware section filtering scheme
- Robust error handling and recovery
- Support of a Program Clock Reference
(PCR) PID
- Automatic detecting and switching of
audio and video PIDs on splice points
• Integrated high performance 54 MHz
CW4001 MiniRISC MIPS CPU
- Host CPU for set-top box; powerful enough
to also handle transport, graphics, ATM SAR
layer processing and other functions
- 4 KB Data (Direct Mapped); 8 KB Instruction
(2-way set associative) Cache
- Timers, interrupt controller
- BBCC- Basic Bus and Cache Controller Unit
- Interfaces to external Set-top components
through Motorola 68K style extension bus
- MIPS-II instruction set compatible
• On-chip DVB, NDS, and Multi2-compliant
descramblers
- Support for transport-level and PES-level
descrambling
- Seamless support of scrambled and
unscrambled data
- Support of up to 12 pairs of 64-bit keys
1 page | ||
| Páginas | Total 2 Páginas | |
| PDF Descargar | [ Datasheet L64108.PDF ] | |
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