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Altera - (EP1S10 - EP1S80) Stratix Device

Numéro de référence EP1S30
Description (EP1S10 - EP1S80) Stratix Device
Fabricant Altera 
Logo Altera 





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EP1S30 fiche technique
Section I. Stratix Device
Family Data Sheet
This section provides designers with the data sheet specifications for
Stratix devices. They contain feature definitions of the internal
architecture, configuration and JTAG boundary-scan testing information,
DC operating conditions, AC timing parameters, a reference to power
consumption, and ordering information for Stratix devices.
This section contains the following chapters:
Chapter 1. Introduction
Chapter 2. Stratix Architecture
Chapter 3. Configuration & Testing
Chapter 4. DC & Switching Characteristics
Chapter 5. Reference & Ordering Information
Revision History The table below shows the revision history for Chapter 1 through
Chapter 5.
Chapter
Date/Version
Changes Made
1 September 2004, v3.1 Updated Table 1–6 on page 1–5.
April 2004, v3.0 Main section page numbers changed on first page.
Changed PCI-X to PCI-X 1.0 in “Features” on page 1–2.
Global change from SignalTap to SignalTap II.
mJanuary 2004, v2.2
.coOctober 2003, v2.1
uJuly 2003, v2.0
The DSP blocks in “Features” on page 1–2 provide dedicated
implementation of multipliers that are now “faster than 300 MHz.”
Updated -5 speed grade device information in Table 1-6.
Add -8 speed grade device information.
Format changes throughout chapter.
www.datasheet4Altera Corporation
Section I–1
Preliminary

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